4 * author: hackbard@hackdaworld.org
6 * number of priorities:
7 * - switch on board power
8 * - allow high speed usb transfer
13 /* constant definitions */
19 /* type definitions */
20 typedef unsigned char u8;
21 typedef unsigned short u16;
22 typedef unsigned int u32;
28 /* general configuration */
29 xdata at 0xe600 volatile u8 CPUCS;
30 xdata at 0xe601 volatile u8 IFCONFIG;
32 /* endpoint configuration */
33 xdata at 0xe60b volatile u8 REVCTL;
34 xdata at 0xe612 volatile u8 EP2CFG;
35 xdata at 0xe614 volatile u8 EP6CFG;
36 xdata at 0xe618 volatile u8 EP2FIFOCFG;
37 xdata at 0xe619 volatile u8 EP4FIFOCFG;
38 xdata at 0xe61a volatile u8 EP6FIFOCFG;
39 xdata at 0xe61b volatile u8 EP8FIFOCFG;
41 /* special funtion registers */
45 /* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
46 * and some others (p. 438).
47 * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
48 #define SYNCDELAY _asm \
49 nop; nop; nop; nop; nop; nop; nop; nop; \
50 nop; nop; nop; nop; nop; nop; nop; nop; \
55 /* high level must be applied to the mosfet gate for power on
57 * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
60 /* configure pin 7 of port d as output */
67 void slave_fifo_init() {
69 /* initialization of the slave fifo, used by external logic (the fpga)
70 * to do usb communication with the host */
72 /* set bit 0 and 1 - fifo slave config */
78 /* p. 180: must be set to 1 */
79 REVCTL|=((1<<0)|(1<<1));
81 /* 8 bit fifo to all endpoints
83 * ('or' of all these bits define port d functionality)
90 /* default indexed flag configuration:
92 * flag a: programmable level
96 * todo: -> fixed configuration
99 /* endpoint configuration:
101 * (assuming 'high bandwidth in' [fpga -> host]
102 * and 'low bandwidth out' [host->fpga] applications)
104 * ep2: bulk in 3x1024
105 * ep6: bulk out 2x512
107 * 0xeb = 1 1 1 0 1 0 1 1 = bulk in 3x1024
108 * 0xa2 = 1 0 1 0 0 0 1 0 = bulk out 2x512
109 * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
117 FIFORESET=0x80; /* nak all transfers */
118 FIFORESET=0x02; /* reset ep2 */
119 FIFORESET=0x06; /* reset ep6 */
120 FIFORESET=0x00; /* restore normal operation */
122 /* auto in/out, no cpu interaction! auto in len = 1024 */
124 EP2AUTOINLENH=(1<<2);
128 /* maybe OUTPKTEND necessary (with skip=1) */
133 /* initialize endpoint 1 (will be used for jtag) */
135 /* endpoint 1 configuration:
137 * default (valid, bulk) fits!
144 /* swicth on power */
147 /* slave fifo init */
155 /* initialize the fx2 */