init of new files (of hdw tank project + some small mods, more to come

...)

diff --git a/led_plex/main.asm b/led_plex/main.asm
new file mode 100644 (file)
index 0000000..cfa8c2e
--- /dev/null
+++ b/led_plex/main.asm
@@ -0,0 +1,129 @@
+; main file of led_plex project
+;
+; author: hackbard@hackdaworld.org
+;
+
+; device specific definition file
+.include "../include/tn2313def.inc"
+
+; defines
+.def   tmp1            = r16
+.def   tmp2            = r17
+.def   uart_rxtx       = r18
+
+;
+; interrupts
+;
+
+; RESET
+rjmp INIT
+
+; INT0
+reti
+
+; INT1
+reti
+
+; T1 CAPT1
+reti
+
+; T1 COMP A
+reti
+
+; T1 OVF1
+rjmp T1_OVF1
+
+; T0 OVF0
+rjmp T0_OVF0
+
+; UART RX
+rjmp UART_RX
+
+; UART UDRE
+reti
+
+; UART TX
+reti
+
+; ANA COMP
+reti
+
+; PCINT
+reti
+
+; T1 COMP B
+reti
+
+; T0 COMP A
+reti
+
+; T0 COMP B
+reti
+
+; USI START
+reti
+
+; USI OVF
+reti
+
+; EE READY
+reti
+
+; WDT OVF
+reti
+
+
+; include control defines
+.include "ctrl.def"
+
+RESET:
+INIT:
+
+       ; port init
+       rcall PORT_INIT
+
+       ; timer init
+       rcall TIMER_INIT
+
+       ; uart init
+       rcall UART_INIT
+
+       ; uart interrupt enable
+       rcall UART_INT_RX_INIT
+
+       ; set stackpointer
+       ldi tmp1,low(RAMEND)
+       out SPL,tmp1
+
+       ; global interrupt enable
+       ;sei 
+
+       ; signal ready output
+       ldi uart_rxtx,0x23
+       rcall UART_TX
+
+MAIN:
+
+       ; loop forever
+       rjmp MAIN
+
+
+; include subroutines
+.include "port.asm"
+.include "timer.asm"
+.include "uart.asm"
+
+
+;
+; interrupt routines
+;
+
+T1_OVF1:
+       reti
+
+T0_OVF0:
+       reti
+
+UART_RX:
+       reti
+

diff --git a/led_plex/uart.asm b/led_plex/uart.asm
new file mode 100644 (file)
index 0000000..e7a5830
--- /dev/null
+++ b/led_plex/uart.asm
@@ -0,0 +1,60 @@
+; uart functions
+
+; default uart settings / 19.2k @ 8 mhz
+; ifndef UART_BR_H
+.equ   UART_BR_H       = 0
+; ifndef UART_BR_L
+.equ   UART_BR_L       = 25
+
+UART_INIT:
+
+       ; baudrate
+       ldi tmp1,UART_BR_H
+       sts UBRR0H,tmp1
+       ldi tmp1,UART_BR_L
+       out UBRR0L,tmp1
+
+       ; enable
+       ldi tmp1,(1<<RXEN)|(1<<TXEN)
+       out UCSR0B,tmp1
+
+       ; frame format -> 8n1
+       ldi tmp1,(1<<UCSZ00)|(1<<UCSZ01)
+       sts UCSR0C,tmp1
+
+       ret
+
+UART_INT_RX_INIT:
+
+       in tmp1,UCSR0B
+       sbr tmp1,(1<<RXCIE0)
+       out UCSR0B,tmp1
+
+       ret
+
+UART_INT_TX_INIT:
+
+       in tmp1,UCSR0B
+       sbr tmp1,(1<<TXCIE0)
+       out UCSR0B,tmp1
+
+       ret
+
+UART_RX:
+
+       ; get/store received byte
+       sbis UCSR0A,RXC0
+               rjmp UART_RX
+       in uart_rxtx,UDR0
+
+       ret
+
+UART_TX:
+
+       ; transmit content of uart_rxtx
+       sbis UCSR0A,UDRE
+               rjmp UART_TX
+       out UDR0,uart_rxtx
+
+       ret
+