cafete backups

[my-code/fpga.git] / fx2 / fx2.c

diff --git a/fx2/fx2.c b/fx2/fx2.c
index ddea734..fcb3dd4 100644 (file)
--- a/fx2/fx2.c
+++ b/fx2/fx2.c
@@ -21,20 +21,146 @@ typedef unsigned char u8;
 typedef unsigned short u16;
 typedef unsigned int u32;
 
-/* fx2 register */
-xdata at 0xb5 volatile u8 OED;
-xdata at 0xb0 volatile u8 IOD;
+/*
+ * fx2 register
+ */
+
+/* general configuration */
+xdata at 0xe600 volatile u8 CPUCS;
+xdata at 0xe601 volatile u8 IFCONFIG;
+
+/* endpoint configuration */
+xdata at 0xe604 volatile u8 FIFORESET;
+xdata at 0xe60b volatile u8 REVCTL;
+xdata at 0xe612 volatile u8 EP2CFG;
+xdata at 0xe613 volatile u8 EP4CFG;
+xdata at 0xe614 volatile u8 EP6CFG;
+xdata at 0xe615 volatile u8 EP8CFG;
+xdata at 0xe618 volatile u8 EP2FIFOCFG;
+xdata at 0xe619 volatile u8 EP4FIFOCFG;
+xdata at 0xe61a volatile u8 EP6FIFOCFG;
+xdata at 0xe61b volatile u8 EP8FIFOCFG;
+xdata at 0xe624 volatile u8 EP6AUTOINLENH;
+xdata at 0xe625 volatile u8 EP6AUTOINLENL;
+
+/* special funtion registers */
+sfr at 0xb5 OED;
+sfr at 0xb0 IOD;
+
+/* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
+ * and some others (p. 438).
+ * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
+#define SYNCDELAY _asm \
+       nop; nop; nop; nop; nop; nop; nop; nop; \
+       nop; nop; nop; nop; nop; nop; nop; nop; \
+       nop; _endasm
 
 void power_on() {
 
+       /* high level must be applied to the mosfet gate for power on
+        *
+        * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
+        */
+
+       /* configure pin 7 of port d as output */
        OED|=(1<<7);
+
+       /* pull it high */
        IOD|=(1<<7);
 }
 
-void main() {
+void slave_fifo_init() {
+
+       /* initialization of the slave fifo, used by external logic (the fpga)
+        * to do usb communication with the host */
+
+       /* set bit 0 and 1 - fifo slave config */       
+       IFCONFIG|=0x03;
+
+       /* async mode */
+       IFCONFIG|=0x04;
+
+       /* p. 180: must be set to 1 */
+       REVCTL|=((1<<0)|(1<<1));
+
+       /* 8 bit fifo to all endpoints
+        *
+        * ('or' of all these bits define port d functionality)
+        */
+       EP2FIFOCFG&=~(1<<0);
+       EP4FIFOCFG&=~(1<<0);
+       EP6FIFOCFG&=~(1<<0);
+       EP8FIFOCFG&=~(1<<0);
+
+       /* default indexed flag configuration:
+        *
+        * flag a: programmable level
+        * flag b: full
+        * flag c: empty
+        *
+        * todo: -> fixed configuration
+        */
+
+       /* endpoint configuration:
+        *
+        * ep2: bulk in 4x512
+        * ep6: bulk out 4x512
+        *
+        * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
+        * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
+        * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
+        */
+       EP2CFG=0xa0;
+       EP4CFG=0x01;
+       EP6CFG=0xe0;
+       EP8CFG=0x01;
+
+       /* reset the fifo */
+       FIFORESET=0x80; /* nak all transfers */
+       FIFORESET=0x02; /* reset ep2 */
+       FIFORESET=0x06; /* reset ep6 */
+       FIFORESET=0x00; /* restore normal operation */
 
-       power_on;
+       /* auto in/out, no cpu interaction! auto in len = 512 */
+       EP2FIFOCFG|=(1<<4);
+       EP6FIFOCFG|=(1<<3);
+       EP6AUTOINLENH=(1<<1);
+       EP6AUTOINLENL=0;
+
+       /* maybe OUTPKTEND necessary (with skip=1) */
+}
+
+void ep1_init() {
+
+       /* initialize endpoint 1 (will be used for jtag) */
+
+       /* endpoint 1 configuration:
+        *
+        * default (valid, bulk) fits!
+        */
+
+}
+
+void fx2_init() {
+
+       /* swicth on power */
+       power_on();
+
+       /* slave fifo init */
+       slave_fifo_init();
+
+       /* ep1_init(); */
 }
 
+void main() {
+
+       /* initialize the fx2 */
+       fx2_init();
 
+       /* do the job ... */
+       while(1) {
        
+       }
+
+}
+