*
* author: hackbard@hackdaworld.org
*
- * number of priorities:
- * - switch on board power
- * - allow high speed usb transfer
+ * feature list:
+ * - switch on board power (done)
+ * - allow high speed bulk usb transfer
* - do jtag
*
*/
/* constant definitions */
-#define TRUE 1
-#define FALSE 0
-#define POWER_ON 1;
-#define POWER_OFF 0;
+#define GET_TDO 0x20
/* type definitions */
typedef unsigned char u8;
xdata at 0xe601 volatile u8 IFCONFIG;
/* endpoint configuration */
+xdata at 0xe604 volatile u8 FIFORESET;
xdata at 0xe60b volatile u8 REVCTL;
+xdata at 0xe610 volatile u8 EP1OUTCFG;
+xdata at 0xe611 volatile u8 EP1INCFG;
xdata at 0xe612 volatile u8 EP2CFG;
+xdata at 0xe613 volatile u8 EP4CFG;
xdata at 0xe614 volatile u8 EP6CFG;
+xdata at 0xe615 volatile u8 EP8CFG;
xdata at 0xe618 volatile u8 EP2FIFOCFG;
xdata at 0xe619 volatile u8 EP4FIFOCFG;
xdata at 0xe61a volatile u8 EP6FIFOCFG;
xdata at 0xe61b volatile u8 EP8FIFOCFG;
+xdata at 0xe620 volatile u8 EP2AUTOINLENH;
+xdata at 0xe621 volatile u8 EP2AUTOINLENL;
+xdata at 0xe624 volatile u8 EP6AUTOINLENH;
+xdata at 0xe625 volatile u8 EP6AUTOINLENL;
+
+/* endpoint control/status */
+xdata at 0xe6a1 volatile u8 EP1OUTCS;
+xdata at 0xe6a2 volatile u8 EP1INCS;
+xdata at 0xe68d volatile u16 EP1OUTBC;
+xdata at 0xe68f volatile u16 EP1INBC;
+
+#define STALL 0x01
+#define BUSY 0x02
+
+/* access to endpoint buffers */
+xdata at 0xe780 volatile u8 EP1OUTBUF[64];
+xdata at 0xe7c0 volatile u8 EP1INBUF[64];
/* special funtion registers */
sfr at 0xb5 OED;
nop; nop; nop; nop; nop; nop; nop; nop; \
nop; _endasm
-void power_on() {
+void power_init() {
- /* high level must be applied to the mosfet gate for power on
+ /* pin 7 of port d connected to mosfet gate controlling the board power
*
* ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
*/
/* configure pin 7 of port d as output */
OED|=(1<<7);
+ SYNCDELAY;
+
+}
+
+void toggle_power() {
+
+ /* toggle high/low state of the mosfet gate */
+
+ if((IOD&(1<<7)))
+ IOD&=~(1<<7);
+ else
+ IOD|=(1<<7);
+
+ SYNCDELAY;
+
+}
+
+void jtag_init() {
+
+ /* pin 5 of port d disables tdi -> tdo forward */
+ OED|=(1<<5);
+ IOD|=(1<<5);
+
+ /* jtag pins:
+ * tdi - pin 0 (input)
+ * tdo - pin 2 (output)
+ * tms - pin 3 (output)
+ * tck - pin 4 (output)
+ */
+ OED|=((1<<2)|(1<<3)|(1<<4));
+ OED&=~(1<<0);
+
+}
+
+void cpu_init() {
+
+ /* cpu initialization: (0x10)
+ * - 48 mhz
+ * - none inverted signal
+ * - no clk out
+ */
+
+ CPUCS=(1<<4);
+ SYNCDELAY;
- /* pull it high */
- IOD|=(1<<7);
}
void slave_fifo_init() {
/* initialization of the slave fifo, used by external logic (the fpga)
* to do usb communication with the host */
- /* set bit 0 and 1 - fifo slave config */
- IFCONFIG|=0x03;
+ /* enable dyn_out and enhanced packet handling (p. 189) */
+ REVCTL=0x03;
+ SYNCDELAY;
- /* async mode */
- IFCONFIG|=0x04;
+ /* internal 48 mhz clock, async, slave fifo */
+ IFCONFIG=0xcb;
+ SYNCDELAY;
- /* p. 180: must be set to 1 */
- REVCTL|=((1<<0)|(1<<1));
-
- /* 8 bit fifo to all endpoints
+ /* endpoint setup:
*
- * ('or' of all these bits define port d functionality)
+ * ep2: bulk out 2x512
+ * ep4: bulk out 2x512
+ * ep6: bulk in 2x512
+ * ep8: bulk in 2x512
*/
- EP2FIFOCFG&=~(1<<0);
- EP4FIFOCFG&=~(1<<0);
- EP6FIFOCFG&=~(1<<0);
- EP8FIFOCFG&=~(1<<0);
+ EP2CFG=0xa2;
+ EP4CFG=0xa0;
+ EP6CFG=0xc2;
+ EP8CFG=0xc0;
+ SYNCDELAY;
+
+ /* reset the fifo */
+ FIFORESET=0x80; /* nak all transfers */
+ SYNCDELAY;
+ FIFORESET=0x02; /* reset ep2 */
+ SYNCDELAY;
+ FIFORESET=0x04; /* reset ep4 */
+ SYNCDELAY;
+ FIFORESET=0x06; /* reset ep6 */
+ SYNCDELAY;
+ FIFORESET=0x08; /* reset ep8 */
+ SYNCDELAY;
+ FIFORESET=0x00; /* restore normal operation */
+ SYNCDELAY;
+
+ /* 8 bit fifo to all endpoints */
+ EP2FIFOCFG=;
+ SYNCDELAY;
+ EP4FIFOCFG=;
+ SYNCDELAY;
+ EP6FIFOCFG=;
+ SYNCDELAY;
+ EP8FIFOCFG=;
+ SYNCDELAY;
/* default indexed flag configuration:
*
* todo: -> fixed configuration
*/
- /* endpoint configuration:
- *
- * (assuming 'high bandwidth in' [fpga -> host]
- * and 'low bandwidth out' [host->fpga] applications)
- *
- * ep2: bulk in 3x1024
- * ep6: bulk out 2x512
- *
- * 0xeb = 1 1 1 0 1 0 1 1 = bulk in 3x1024
- * 0xa2 = 1 0 1 0 0 0 1 0 = bulk out 2x512
- * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
- */
- EP2CFG=0xeb;
- EP4CFG=0x01;
- EP6CFG=0xa2;
- EP8CFG=0x01;
+ /* auto in/out, no cpu interaction! auto in len = 512 */
+ EP2FIFOCFG|=(1<<4);
+ SYNCDELAY;
+ EP6FIFOCFG|=(1<<3);
+ SYNCDELAY;
+ EP6AUTOINLENH=(1<<1);
+ SYNCDELAY;
+ EP6AUTOINLENL=0;
+ SYNCDELAY;
- /* reset the fifo */
- FIFORESET=0x80; /* nak all transfers */
- FIFORESET=0x02; /* reset ep2 */
- FIFORESET=0x06; /* reset ep6 */
- FIFORESET=0x00; /* restore normal operation */
-
- /* auto in/out, no cpu interaction! auto in len = 1024 */
- EP2FIFOCFG|=(1<<3);
- EP2AUTOINLENH=(1<<2);
- EP2AUTOINLENL=0;
- EP6FIFOCFG|=(1<<4);
-
- /* maybe OUTPKTEND necessary (with skip=1) */
}
void ep1_init() {
- /* initialize endpoint 1 (will be used for jtag) */
+ /* initialize endpoint 1
+ *
+ * used for jtag & control
+ */
/* endpoint 1 configuration:
*
* default (valid, bulk) fits!
*/
+ /* arm ep1out, clear ep1out and ep1in stall bit */
+ EP1OUTBC=0;
+ EP1OUTCS&=~STALL;
+ EP1INCS&=~STALL;
+
}
void fx2_init() {
- /* swicth on power */
- power_on();
+ /* syncdelay */
+ SYNCDELAY;
+
+ /* cpu init */
+ cpu_init();
+
+ /* power init & power on */
+ power_init();
+ toggle_power();
/* slave fifo init */
slave_fifo_init();
- /* ep1_init(); */
+ /* ep1 init */
+ ep1_init();
+
+ /* jtag init */
+ jtag_init();
}
void main() {
+ u8 buf,set;
+
/* initialize the fx2 */
fx2_init();
- /* do the job ... */
+ /* jtag by polling ep1 */
+
while(1) {
-
+ if(!(EP1OUTCS&BUSY)) {
+ set=IOD;
+ buf=EP1OUTBUF[0];
+ IOD=(IOD&(~0x1c))|(buf&0x1c);
+ EP1OUTBC=1;
+ }
+ if(!(EP1INCS&BUSY)) {
+ EP1INBUF[0]=IOD&0x01;
+ EP1INBC=1;
+ }
}
}
projects / my-code / fpga.git / blobdiff