more control

[my-code/atmel.git] / monolyzer / main.asm

diff --git a/monolyzer/main.asm b/monolyzer/main.asm
index 97b4d95..e17e9a7 100644 (file)
--- a/monolyzer/main.asm
+++ b/monolyzer/main.asm
@@ -13,6 +13,7 @@
 .def   tmp2            = r17
 .def   uart_rxtx       = r18
 .def   count           = r19
+.def   state           = r20
 
 ;
 ; interrupts
@@ -22,7 +23,7 @@
 rjmp INIT
 
 ; INT0
-reti
+rjmp INT0_IR
 
 ; INT1
 reti
@@ -34,13 +35,13 @@ reti
 reti
 
 ; T1 OVF1
-reti
+rjmp T1_OVF_IR
 
 ; T0 OVF0
-rjmp T0_OVF
+reti
 
 ; UART RX
-rjmp UART_RECEIVE
+reti
 
 ; UART UDRE
 reti
@@ -85,18 +86,12 @@ INIT:
        ; gio port init
        rcall PORT_INIT
 
-       ; timer0 init
-       rcall TIMER0_INIT
-
-       ; timer0 interrupt enable
-       rcall TIMER0_INT_INIT
+       ; timer1 init
+       rcall TIMER1_INIT
 
        ; uart init
        rcall UART_INIT
 
-       ; uart interrupt enable
-       rcall UART_INT_RX_INIT
-
        ; zero and one initialization
        ldi tmp1,0
        mov zero,tmp1
@@ -108,49 +103,141 @@ INIT:
        out SPL,tmp1
 
        ; more init
-       ldi count,0x21
+       ldi count,0
+       ldi state,0
+
+       ; storage pointer
+       ldi ZL,low(STORAGE)
+       ldi ZH,high(STORAGE)
 
        ; signal ready output
-       ldi uart_rxtx,0x68
+       ldi uart_rxtx,0x72
        rcall UART_TX
 
+       ; external interrupt enable
+       rcall INT0_IR_CONF_INIT
+       rcall INT0_IR_ENABLE
+
        ; global interrupt enable
        sei 
 
 MAIN:
 
-WAIT_FOR_HIGH:
-       ; start as soon as we get a high signal
+SAMPLE:
+
+       ; sample as long as there is storage capacity
+       sbrs state,0
+       rjmp SAMPLE
+
+       ; disable interrupts
+       rcall INT0_IR_DISABLE
+       rcall TIMER1_INT_DISABLE
 
-       rjmp WAIT_FOR_HIGH
+       ; signal finish
+       ldi uart_rxtx,0x66
+       rcall UART_TX
+
+IDLE:
+
+       ; wait for commands via uart
+       rcall UART_RX
+
+       ; decode instruction
+       cpi uart_rxtx,0x52
+       breq RESET
+       cpi uart_rxtx,0x54
+       breq TRANSFER
+
+       rjmp IDLE
+
+TRANSFER:
+
+       ; reset storage pointer
+       ldi ZL,low(STORAGE)
+       ldi ZH,high(STORAGE)
+       ldi tmp1,0
+
+       ; transmit number of sampled words
+       mov uart_rxtx,count
+       rcall UART_TX
 
+TRANSFER_LOOP:
+
+       ; transmit storage
+       ld uart_rxtx,Z+
+       rcall UART_TX
+
+       ; count sent data
+       add tmp1,one
+
+       ; check amount of sent data
+       cp tmp1,count
+       breq IDLE
+
+       rjmp TRANSFER_LOOP
 
 ; include subroutines
 .include "port.asm"
 .include "timer.asm"
 .include "uart.asm"
 
-
 ;
 ; interrupt routines
 ;
 
-T0_OVF:
+INT0_IR:
 
        ; debug output
-       cbi PORTD,3
+       ; cbi PORTD,3
+
+       ; get timer value
+       in tmp1,TCNT1L
+       in tmp2,TCNT1H
+
+       ; check for initial or running state
+       cpi state,0
+       brne INT0_RUN
 
-       ; read port
+       ; configure interrupt for running state
+       rcall INT0_IR_CONF_RUN
+       ldi state,1
+
+       ; reset timer and start ovf interrupt
+       ldi tmp1,0
+       out TCNT1H,tmp1
+       out TCNT1L,tmp1
+       rcall TIMER1_INT_ENABLE
 
-       ; store another byte into sram
+       rjmp EXIT_IR
 
+INT0_RUN:
+
+       ; write timer value into sram
+       st Z+,tmp2
+       st Z+,tmp1
+
+       ; inc counter
+       add count,one
+
+       ; check for left capacity
+       cpi count,55
+       brne EXIT_IR
+
+       ; exit sampling
+       ldi state,0
+
+EXIT_IR:
 
        ; debug output
-       sbi PORTD,3
-       
+       ; sbi PORTD,3
+
        reti
 
-UART_RECEIVE:
+T1_OVF_IR:
+
+       ; exit sampling
+       ldi state,0
+
        reti
 
 
@@ -160,6 +247,5 @@ UART_RECEIVE:
 
 .dseg
 
-DATA_STORAGE: .byte 8
-
+STORAGE: .byte 110