--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"tiny26def.inc"\r
+;* Title :Register/Bit Definitions for the ATtiny26\r
+;* Date :April 16th, 2002\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-mail :support@atmel.no\r
+;* Target MCU :ATtiny26\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATtiny26\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3F\r
+.equ SP =$3D\r
+.equ GIMSK =$3B\r
+.equ GIFR =$3A\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ TCCR1A =$30\r
+.equ TCCR1B =$2F\r
+.equ TCNT1 =$2E\r
+.equ OCR1A =$2D\r
+.equ OCR1B =$2C\r
+.equ OCR1C =$2B\r
+.equ PLLCSR =$29\r
+.equ WDTCR =$21\r
+.equ EEAR =$1E\r
+.equ EEDR =$1D\r
+.equ EECR =$1C\r
+.equ PORTA =$1B\r
+.equ DDRA =$1A\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ USIDR =$0F\r
+.equ USISR =$0E\r
+.equ USICR =$0D\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+\r
+;***** Bit Definitions\r
+;***** GIMSK *****\r
+.equ INT0 =6\r
+.equ PCIE1 =5\r
+.equ PCIE0 =4\r
+\r
+;***** GIFR ******\r
+.equ INTF0 =6\r
+.equ PCIF =5\r
+\r
+;***** TIMSK *****\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ TOIE1 =2\r
+.equ TOIE0 =1\r
+\r
+;***** TIFR ******\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ TOV1 =2\r
+.equ TOV0 =1\r
+\r
+;***** MCUCR ***** \r
+.equ PUD =6\r
+.equ SE =5\r
+.equ SM1 =4\r
+.equ SM0 =3\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;***** MCUSR ***** \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;***** TCCR0 *****\r
+.equ PSR0 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;***** OSCCAL ****\r
+.equ OSCCAL4 =4\r
+.equ OSCCAL3 =3\r
+.equ OSCCAL2 =2\r
+.equ OSCCAL1 =1\r
+.equ OSCCAL0 =0\r
+\r
+;***** TCCR1A ****\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM1A =1\r
+.equ PWM1B =0\r
+\r
+;***** TCCR1B **** \r
+.equ CTC1 =7\r
+.equ PSR1 =6\r
+.equ CS13 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;***** PLLCSR ****\r
+.equ PCKE =2\r
+.equ PLLE =1\r
+.equ PLOCK =0\r
+\r
+;***** WDTCR *****\r
+.equ WDCE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;***** EEAR ******\r
+.equ EEAR6 =6\r
+.equ EEAR5 =5\r
+.equ EEAR4 =4\r
+.equ EEAR3 =3\r
+.equ EEAR2 =2\r
+.equ EEAR1 =1\r
+.equ EEAR0 =0\r
+\r
+;***** EECR ******\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;***** PORTA ***** \r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+.equ PORTA7 =7\r
+.equ PORTA6 =6\r
+.equ PORTA5 =5\r
+.equ PORTA4 =4\r
+.equ PORTA3 =3\r
+.equ PORTA2 =2\r
+.equ PORTA1 =1\r
+.equ PORTA0 =0\r
+\r
+;***** DDRA ******\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;***** PINA ******\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;***** PORTB ***** \r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ PORTB7 =7\r
+.equ PORTB6 =6\r
+.equ PORTB5 =5\r
+.equ PORTB4 =4\r
+.equ PORTB3 =3\r
+.equ PORTB2 =2\r
+.equ PORTB1 =1\r
+.equ PORTB0 =0\r
+\r
+;***** DDRB ******\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;***** PINB ******\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;***** USISR *****\r
+.equ USISIF =7\r
+.equ USIOIF =6\r
+.equ USIPF =5\r
+.equ USIDC =4\r
+.equ USICNT3 =3\r
+.equ USICNT2 =2\r
+.equ USICNT1 =1\r
+.equ USICNT0 =0\r
+\r
+;***** USICR *****\r
+.equ USISIE =7\r
+.equ USIOIE =6\r
+.equ USIWM1 =5\r
+.equ USIWM0 =4\r
+.equ USICS1 =3\r
+.equ USICS0 =2\r
+.equ USICLK =1\r
+.equ USITC =0\r
+\r
+;***** ACSR ******\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACME =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;***** ADMUX *****\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;***** ADCSR *****\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF\r
+\r
+.equ INT0addr =$001 ;External Interrupt0 Vector Address\r
+.equ IOPINSaddr =$002 ;Pin change interrupt\r
+.equ OC1Aaddr =$003 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr =$004 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr =$005 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr =$006 ;Overflow0 Interrupt Vector Address\r
+.equ USI_STARTaddr =$007 ;Universal Seria Bus Start Interrupt Address\r
+.equ USI_OVFaddr =$008 ;Universal Seria Bus Overflow Interrupt Address\r
+.equ ERDYaddr =$009 ;EEPROM Ready Interrupt Vector Address\r
+.equ ACIaddr =$00A ;Analog Comparator Interrupt Vector Address\r
+.equ ADCCaddr =$00B ;ADC conversion complete Interrupt Vector Address\r
projects / my-code / atmel.git / blobdiff