--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m8535def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega8535\r
+;* Date : April 16th, 2002\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :support@atmel.no\r
+;* Target MCU :ATmega8535\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega8535\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ OCR0 =$3c\r
+.equ GIMSK =$3b\r
+.equ GICR =$3b ;new name for GIMSK\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ I2CR =$36\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ;For compatibility, \r
+.equ MCUCSR =$34 ;keep both names until further\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRH =$20 ;Note! UCSRC equals UBRRH\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UCSRC =$20 ;Note! UCSRC equals UBRRH\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSRA =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ I2DR =$03\r
+.equ I2AR =$02\r
+.equ I2SR =$01\r
+.equ I2BR =$00\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+\r
+;***** Bit definitions***** \r
+;GICR\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+.equ IVSEL =1 ; interrupt vector select\r
+.equ IVCE =0 ; interrupt vector change enable\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+\r
+;TIMSK\r
+.equ TOIE0 =0\r
+.equ OCIE0 =1\r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+;TIFR\r
+.equ TOV0 =0\r
+.equ OCF0 =1\r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ RWWSB =6\r
+.equ RWWSRE =4\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;MCUCR\r
+.equ SM2 =7\r
+.equ SE =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUCSR\r
+.equ ISC2 =6\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ PWM0 =6 ; OBSOLETE! Use WGM00\r
+.equ WGM00 =6\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ CTC0 =3 ; OBSOLETE! Use WGM01\r
+.equ WGM01 =3 \r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 =0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 =1\r
+.equ WGM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3 ; OBSOLETE! Use WGM12\r
+.equ CTC11 =4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 =3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 =4\r
+.equ WGM12 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6 ; OBSOLETE! Use WGM20\r
+.equ WGM20 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3 ; OBSOLETE! Use WGM21\r
+.equ WGM21 =3 \r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;SFIOR\r
+.equ ADTS2 =7\r
+.equ ADTS1 =6\r
+.equ ADTS0 =5\r
+.equ ADHSM =4\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+;WDTCR\r
+.equ WDCE =4\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3 ; old name kept for compatibilty\r
+.equ DOR =3\r
+.equ PE =2 ; old name kept for compatibilty\r
+.equ UPE =2\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+;UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;UCSRC\r
+.equ URSEL =7\r
+.equ UMSEL =6\r
+.equ UPM1 =5\r
+.equ UPM0 =4\r
+.equ USBS =3\r
+.equ UCSZ1 =2\r
+.equ UCSZ0 =1\r
+.equ UCPOL =0\r
+ \r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSRA\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADATE =5 \r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+;I2CR\r
+.equ I2INT =7\r
+.equ I2EA =6\r
+.equ I2STA =5\r
+.equ I2STO =4\r
+.equ I2WC =3\r
+.equ ENI2C =2\r
+.equ I2EN =2\r
+.equ I2C_TST =1 ;Present in core test mode only. Write Only.\r
+.equ I2IE =0\r
+\r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+.equ TWI_TST =1 ;Present in core test mode only. Write Only.\r
+.equ TWIE =0\r
+\r
+;I2AR\r
+.equ I2GCE =0\r
+\r
+; TWAR\r
+.equ TWA6 =7\r
+.equ TWA5 =6\r
+.equ TWA4 =5\r
+.equ TWA3 =4\r
+.equ TWA2 =3\r
+.equ TWA1 =2\r
+.equ TWA0 =1\r
+.equ TWGCE =0\r
+\r
+; TWSR\r
+.equ TWS7 =7\r
+.equ TWS6 =6\r
+.equ TWS5 =5\r
+.equ TWS4 =4\r
+.equ TWS3 =3\r
+.equ TWS2 =2\r
+.equ TWS1 =1\r
+.equ TWS0 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$25F\r
+ ; byte groups\r
+ ; /\/--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b00111110000000 ;($0F80) smallest boot block is 128W\r
+.equ SECONDBOOTSTART =0b00111100000000 ;($0F00) 2'nd boot block size is 256W\r
+.equ THIRDBOOTSTART =0b00111000000000 ;($0E00) third boot block size is 512W\r
+.equ LARGEBOOTSTART =0b00110000000000 ;($0C00) largest boot block is 1KW\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =32 ;number of WORDS in a page\r
+.equ FLASHEND =$fff\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ OC2addr =$003 ;Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$004 ;Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$005 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$006 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$007 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$008 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$009 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$00a ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$00b ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00c ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00d ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$00e ;ADC Interrupt Vector Address\r
+.equ ERDYaddr=$00f ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$010 ;Analog Comparator Interrupt Vector Address\r
+.equ TWIaddr =$011 ;Irq. vector address for Two-Wire Interface\r
+.equ I2Caddr =$011 ; Irq. vector address for Inter Intergrated Circuit interface\r
+.equ INT2addr=$012 ;External Interrupt2 Vector Address\r
+.equ OC0addr =$013 ;Output Compare0 Interrupt Vector Address\r
+.equ SPMRaddr=$014 ;Store Program Memory Ready Interrupt Vector Address\r
projects / my-code / atmel.git / blobdiff