--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number : AVR000\r
+;* File Name : "m64def.inc"\r
+;* Title : Register/Bit Definitions for the ATmega604\r
+;* Date : April 16th, 2002\r
+;* Version : 1.0\r
+;* Support telephone : +47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax : +47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail : support@atmel.no\r
+;* Target MCU : ATmega64\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;**** Specify Device ****\r
+.device ATmega64\r
+\r
+;*****************************************************************************\r
+; I/O Register Definitions\r
+;*****************************************************************************\r
+\r
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****\r
+.equ UCSR1C = $9D\r
+.equ UDR1 = $9C\r
+.equ UCSR1A = $9B\r
+.equ UCSR1B = $9A\r
+.equ UBRR1L = $99\r
+.equ UBRR1H = $98\r
+.equ UCSR0C = $95\r
+.equ UBRR0H = $90\r
+.equ ADCSRB = $8E\r
+.equ TCCR3C = $8C\r
+.equ TCCR3A = $8B\r
+.equ TCCR3B = $8A\r
+.equ TCNT3H = $89\r
+.equ TCNT3L = $88\r
+.equ OCR3AH = $87\r
+.equ OCR3AL = $86\r
+.equ OCR3BH = $85\r
+.equ OCR3BL = $84\r
+.equ OCR3CH = $83\r
+.equ OCR3CL = $82\r
+.equ ICR3H = $81\r
+.equ ICR3L = $80\r
+.equ ETIMSK = $7D\r
+.equ ETIFR = $7C\r
+.equ TCCR1C = $7A\r
+.equ OCR1CH = $79\r
+.equ OCR1CL = $78\r
+.equ I2CR = $74\r
+.equ I2DR = $73\r
+.equ I2AR = $72\r
+.equ I2SR = $71\r
+.equ I2BR = $70\r
+.equ TWCR = $74\r
+.equ TWDR = $73\r
+.equ TWAR = $72\r
+.equ TWSR = $71\r
+.equ TWBR = $70\r
+.equ OSCCAL = $6F\r
+.equ XMCRA = $6D\r
+.equ XMCRB = $6C\r
+.equ EICRA = $6A\r
+.equ SPMCSR = $68\r
+.equ SPMCR = $68 ; old name for SPMCSR\r
+.equ PORTG = $65\r
+.equ DDRG = $64\r
+.equ PING = $63\r
+.equ PORTF = $62\r
+.equ DDRF = $61\r
+\r
+;**** I/O Register Definitions ($3F-$00) ****\r
+.equ SREG = $3F\r
+.equ SPH = $3E\r
+.equ SPL = $3D\r
+.equ XDIV = $3C\r
+.equ EICRB = $3A\r
+.equ EIMSK = $39\r
+.equ GIMSK = $39 ; old name for EIMSK\r
+.equ GICR = $39 ; old name for EIMSK\r
+.equ EIFR = $38\r
+.equ GIFR = $38 ; old name for EIFR\r
+.equ TIMSK = $37\r
+.equ TIFR = $36\r
+.equ MCUCR = $35\r
+.equ MCUCSR = $34\r
+.equ TCCR0 = $33\r
+.equ TCNT0 = $32\r
+.equ OCR0 = $31\r
+.equ ASSR = $30\r
+.equ TCCR1A = $2F\r
+.equ TCCR1B = $2E\r
+.equ TCNT1H = $2D\r
+.equ TCNT1L = $2C\r
+.equ OCR1AH = $2B\r
+.equ OCR1AL = $2A\r
+.equ OCR1BH = $29\r
+.equ OCR1BL = $28\r
+.equ ICR1H = $27\r
+.equ ICR1L = $26\r
+.equ TCCR2 = $25\r
+.equ TCNT2 = $24\r
+.equ OCR2 = $23\r
+.equ OCDR = $22 ; New\r
+.equ WDTCR = $21\r
+.equ SFIOR = $20 ; New\r
+.equ EEARH = $1F\r
+.equ EEARL = $1E\r
+.equ EEDR = $1D\r
+.equ EECR = $1C\r
+.equ PORTA = $1B\r
+.equ DDRA = $1A\r
+.equ PINA = $19\r
+.equ PORTB = $18\r
+.equ DDRB = $17\r
+.equ PINB = $16\r
+.equ PORTC = $15\r
+.equ DDRC = $14 ; New\r
+.equ PINC = $13 ; New\r
+.equ PORTD = $12\r
+.equ DDRD = $11\r
+.equ PIND = $10\r
+.equ SPDR = $0F\r
+.equ SPSR = $0E\r
+.equ SPCR = $0D\r
+.equ UDR0 = $0C\r
+.equ UCSR0A = $0B\r
+.equ UCSR0B = $0A\r
+.equ UBRR0L = $09\r
+.equ ACSR = $08\r
+.equ ADMUX = $07\r
+.equ ADCSRA = $06 \r
+.equ ADCSR = $06\r
+.equ ADCH = $05\r
+.equ ADCL = $04\r
+.equ PORTE = $03\r
+.equ DDRE = $02\r
+.equ PINE = $01\r
+.equ PINF = $00\r
+\r
+\r
+;*****************************************************************************\r
+; Bit Definitions\r
+;*****************************************************************************\r
+\r
+; **** MCU Control ****\r
+; **** MCUCR ****\r
+.equ SRE = 7 \r
+.equ SRW10 = 6\r
+.equ SE = 5\r
+.equ SM1 = 4\r
+.equ SM0 = 3\r
+.equ SM2 = 2\r
+.equ IVSEL = 1\r
+.equ IVCE = 0\r
+\r
+; **** MCUCSR ****\r
+.equ JTD = 7 \r
+.equ JTRF = 4 \r
+.equ WDRF = 3\r
+.equ BORF = 2\r
+.equ EXTRF = 1\r
+.equ PORF = 0\r
+\r
+; **** XMCRA ****\r
+.equ SRL2 = 6 \r
+.equ SRL1 = 5\r
+.equ SRL0 = 4\r
+.equ SRW01 = 3\r
+.equ SRW00 = 2\r
+.equ SRW11 = 1\r
+\r
+; **** XMCRB ****\r
+.equ XMBK = 7 \r
+.equ XMM2 = 2\r
+.equ XMM1 = 1\r
+.equ XMM0 = 0\r
+\r
+; **** SPMCSR ****\r
+.equ SPMIE = 7 \r
+.equ ASB = 6 ; backwards compatiblity\r
+.equ ASRE = 4 ; backwards compatiblity\r
+.equ RWWSB = 6\r
+.equ RWWSRE = 4 \r
+.equ BLBSET = 3\r
+.equ PGWRT = 2\r
+.equ PGERS = 1\r
+.equ SPMEN = 0\r
+\r
+; **** OCDR ****\r
+.equ IDRD = 7 \r
+.equ OCDR6 = 6\r
+.equ OCDR5 = 5\r
+.equ OCDR4 = 4 \r
+.equ OCDR3 = 3\r
+.equ OCDR2 = 2\r
+.equ OCDR1 = 1\r
+.equ OCDR0 = 0\r
+\r
+; **** XDIV ****\r
+.equ XDIVEN = 7 \r
+.equ XDIV6 = 6\r
+.equ XDIV5 = 5\r
+.equ XDIV4 = 4\r
+.equ XDIV3 = 3\r
+.equ XDIV2 = 2\r
+.equ XDIV1 = 1\r
+.equ XDIV0 = 0\r
+\r
+; **** SFIOR ****\r
+.equ TSM = 7 \r
+.equ ADHSM = 4\r
+.equ ACME = 3\r
+.equ PUD = 2\r
+.equ PSR0 = 1\r
+.equ PSR1 = 0\r
+.equ PSR2 = 0\r
+.equ PSR3 = 0\r
+.equ PSR321 = 0 \r
+\r
+; **** Analog to Digital Converter ****\r
+; **** ADCSR ****\r
+.equ ADEN = 7 \r
+.equ ADSC = 6\r
+.equ ADATE = 5\r
+.equ ADFR = 5\r
+.equ ADIF = 4\r
+.equ ADIE = 3\r
+.equ ADPS2 = 2\r
+.equ ADPS1 = 1\r
+.equ ADPS0 = 0\r
+\r
+; **** ADMUX ****\r
+.equ REFS1 = 7 \r
+.equ REFS0 = 6\r
+.equ ADLAR = 5\r
+.equ MUX4 = 4\r
+.equ MUX3 = 3\r
+.equ MUX2 = 2\r
+.equ MUX1 = 1\r
+.equ MUX0 = 0\r
+\r
+; **** ADCSRB ****\r
+.equ ADTS2 = 2 \r
+.equ ADTS1 = 1\r
+.equ ADTS0 = 0 \r
+\r
+;**** Analog Comparator ****\r
+; **** ACSR ****\r
+.equ ACD = 7 \r
+.equ ACBG = 6\r
+.equ ACO = 5\r
+.equ ACI = 4\r
+.equ ACIE = 3\r
+.equ ACIC = 2\r
+.equ ACIS1 = 1\r
+.equ ACIS0 = 0\r
+ \r
+\r
+; **** External Interrupts ****\r
+; **** EIMSK ****\r
+.equ INT7 = 7 \r
+.equ INT6 = 6\r
+.equ INT5 = 5\r
+.equ INT4 = 4\r
+.equ INT3 = 3\r
+.equ INT2 = 2\r
+.equ INT1 = 1\r
+.equ INT0 = 0\r
+\r
+; **** EIFR ****\r
+.equ INTF7 = 7 \r
+.equ INTF6 = 6\r
+.equ INTF5 = 5\r
+.equ INTF4 = 4\r
+.equ INTF3 = 3\r
+.equ INTF2 = 2\r
+.equ INTF1 = 1\r
+.equ INTF0 = 0\r
+\r
+; **** EICRB ****\r
+.equ ISC71 = 7 \r
+.equ ISC70 = 6\r
+.equ ISC61 = 5\r
+.equ ISC60 = 4\r
+.equ ISC51 = 3\r
+.equ ISC50 = 2\r
+.equ ISC41 = 1\r
+.equ ISC40 = 0\r
+\r
+; **** EICRA ****\r
+.equ ISC31 = 7 \r
+.equ ISC30 = 6\r
+.equ ISC21 = 5\r
+.equ ISC20 = 4\r
+.equ ISC11 = 3\r
+.equ ISC10 = 2\r
+.equ ISC01 = 1\r
+.equ ISC00 = 0\r
+\r
+; **** Timer Interrupts ****\r
+; **** TIMSK ****\r
+.equ OCIE2 = 7 \r
+.equ TOIE2 = 6\r
+.equ TICIE1 = 5\r
+.equ OCIE1A = 4\r
+.equ OCIE1B = 3\r
+.equ TOIE1 = 2\r
+.equ OCIE0 = 1\r
+.equ TOIE0 = 0\r
+\r
+; **** ETIMSK ****\r
+.equ TICIE3 = 5 \r
+.equ OCIE3A = 4\r
+.equ OCIE3B = 3\r
+.equ TOIE3 = 2\r
+.equ OCIE3C = 1\r
+.equ OCIE1C = 0\r
+\r
+; **** TIFR ****\r
+.equ OCF2 = 7 \r
+.equ TOV2 = 6\r
+.equ ICF1 = 5\r
+.equ OCF1A = 4\r
+.equ OCF1B = 3\r
+.equ TOV1 = 2\r
+.equ OCF0 = 1\r
+.equ TOV0 = 0\r
+\r
+; **** ETIFR ****\r
+.equ ICF3 = 5 \r
+.equ OCF3A = 4\r
+.equ OCF3B = 3\r
+.equ TOV3 = 2\r
+.equ OCF3C = 1\r
+.equ OCF1C = 0\r
+\r
+; **** Asynchronous Timer ****\r
+; **** ASSR ****\r
+.equ AS0 = 3 \r
+.equ TCN0UB = 2\r
+.equ OCR0UB = 1\r
+.equ TCR0UB = 0\r
+\r
+; **** Timer 0 ****\r
+; **** TCCR0 ****\r
+.equ FOC0 = 7 \r
+.equ PWM0 = 6\r
+.equ WGM00 = 6 \r
+.equ COM01 = 5\r
+.equ COM00 = 4\r
+.equ CTC0 = 3\r
+.equ WGM01 = 3\r
+.equ CS02 = 2\r
+.equ CS01 = 1\r
+.equ CS00 = 0\r
+\r
+; **** Timer 1 ****\r
+; **** TCCR1A ****\r
+.equ COM1A1 = 7 \r
+.equ COM1A0 = 6\r
+.equ COM1B1 = 5\r
+.equ COM1B0 = 4\r
+.equ COM1C1 = 3\r
+.equ COM1C0 = 2\r
+.equ PWM11 = 1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 = 0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 = 1\r
+.equ WGM10 = 0\r
+\r
+; **** TCCR1B ****\r
+.equ ICNC1 = 7 \r
+.equ ICES1 = 6\r
+.equ CTC11 = 4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 = 3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 = 4\r
+.equ WGM12 = 3\r
+.equ CS12 = 2\r
+.equ CS11 = 1\r
+.equ CS10 = 0\r
+\r
+; **** TCCR1C ****\r
+.equ FOC1A = 7 \r
+.equ FOC1B = 6\r
+.equ FOC1C = 5\r
+\r
+; **** Timer 2 ****\r
+; **** TCCR2 ****\r
+.equ FOC2 = 7 \r
+.equ PWM2 = 6\r
+.equ WGM20 = 6 \r
+.equ COM21 = 5\r
+.equ COM20 = 4\r
+.equ CTC2 = 3\r
+.equ WGM21 = 3\r
+.equ CS22 = 2\r
+.equ CS21 = 1\r
+.equ CS20 = 0\r
+\r
+; **** Timer 3 ****\r
+; **** TCCR3A ****\r
+.equ COM3A1 = 7 \r
+.equ COM3A0 = 6\r
+.equ COM3B1 = 5\r
+.equ COM3B0 = 4\r
+.equ COM3C1 = 3\r
+.equ COM3C0 = 2\r
+.equ PWM31 = 1 ; OBSOLETE! Use WGM31\r
+.equ PWM30 = 0 ; OBSOLETE! Use WGM30\r
+.equ WGM31 = 1\r
+.equ WGM30 = 0\r
+\r
+; **** TCCR3B **** \r
+.equ ICNC3 = 7 \r
+.equ ICES3 = 6\r
+.equ CTC31 = 4 ; OBSOLETE! Use WGM33\r
+.equ CTC30 = 3 ; OBSOLETE! Use WGM32\r
+.equ WGM33 = 4\r
+.equ WGM32 = 3\r
+.equ CS32 = 2\r
+.equ CS31 = 1\r
+.equ CS30 = 0\r
+\r
+; **** TCCR3C ****\r
+.equ FOC3A = 7 \r
+.equ FOC3B = 6\r
+.equ FOC3C = 5\r
+\r
+; **** Watchdog Timer ****\r
+; **** WDTCR ****\r
+.equ WDCE = 4 \r
+.equ WDTOE = 4 ; For Mega103 compability\r
+.equ WDE = 3\r
+.equ WDP2 = 2\r
+.equ WDP1 = 1\r
+.equ WDP0 = 0\r
+\r
+; **** EEPROM Control Register ****\r
+; **** EECR ****\r
+.equ EERIE = 3 \r
+.equ EEMWE = 2\r
+.equ EEWE = 1\r
+.equ EERE = 0\r
+\r
+; **** USART 0 and USART 1 ****\r
+; **** (UCSRA0/1) ****\r
+.equ RXC = 7 \r
+.equ TXC = 6\r
+.equ UDRE = 5\r
+.equ FE = 4\r
+.equ DOR = 3\r
+.equ PE = 2 ; OBSOLETED!\r
+.equ U2X = 1\r
+.equ MPCM = 0\r
+\r
+; **** (UCSR0A) ****\r
+.equ RXC0 = 7 \r
+.equ TXC0 = 6\r
+.equ UDRE0 = 5\r
+.equ FE0 = 4\r
+.equ DOR0 = 3\r
+.equ UPE0 = 2\r
+.equ U2X0 = 1\r
+.equ MPCM0 = 0\r
+\r
+; **** (UCSR1A) ****\r
+.equ RXC1 = 7 \r
+.equ TXC1 = 6\r
+.equ UDRE1 = 5\r
+.equ FE1 = 4\r
+.equ DOR1 = 3\r
+.equ UPE1 = 2\r
+.equ U2X1 = 1\r
+.equ MPCM1 = 0\r
+\r
+; **** (UCSRB0/1) ****\r
+.equ RXCIE = 7 \r
+.equ TXCIE = 6\r
+.equ UDRIE = 5\r
+.equ RXEN = 4\r
+.equ TXEN = 3\r
+.equ UCSZ2 = 2\r
+.equ RXB8 = 1\r
+.equ TXB8 = 0\r
+\r
+; **** (UCSR0B) ****\r
+.equ RXCIE0 = 7 \r
+.equ TXCIE0 = 6\r
+.equ UDRIE0 = 5\r
+.equ RXEN0 = 4\r
+.equ TXEN0 = 3\r
+.equ UCSZ02 = 2\r
+.equ RXB80 = 1\r
+.equ TXB80 = 0\r
+\r
+; **** (UCSR1B) ****\r
+.equ RXCIE1 = 7 \r
+.equ TXCIE1 = 6\r
+.equ UDRIE1 = 5\r
+.equ RXEN1 = 4\r
+.equ TXEN1 = 3\r
+.equ UCSZ12 = 2\r
+.equ RXB81 = 1\r
+.equ TXB81 = 0\r
+\r
+; **** (UCSRC0/1) ****\r
+.equ UMSEL = 6 \r
+.equ UPM1 = 5\r
+.equ UPM0 = 4\r
+.equ USBS = 3\r
+.equ UCSZ1 = 2\r
+.equ UCSZ0 = 1\r
+.equ UCPOL = 0\r
+\r
+; **** (UCSR0C) ****\r
+.equ UMSEL0 = 6 \r
+.equ UPM01 = 5\r
+.equ UPM00 = 4\r
+.equ USBS0 = 3\r
+.equ UCSZ01 = 2\r
+.equ UCSZ00 = 1\r
+.equ UCPOL0 = 0\r
+\r
+; **** (UCSR1C) ****\r
+.equ UMSEL1 = 6 \r
+.equ UPM11 = 5\r
+.equ UPM10 = 4\r
+.equ USBS1 = 3\r
+.equ UCSZ11 = 2\r
+.equ UCSZ10 = 1\r
+.equ UCPOL1 = 0\r
+\r
+ \r
+; **** SPI ****\r
+; **** SPCR ****\r
+.equ SPIE = 7 \r
+.equ SPE = 6\r
+.equ DORD = 5\r
+.equ MSTR = 4\r
+.equ CPOL = 3\r
+.equ CPHA = 2\r
+.equ SPR1 = 1\r
+.equ SPR0 = 0\r
+\r
+; **** SPSR ****\r
+.equ SPIF = 7 \r
+.equ WCOL = 6\r
+.equ SPI2X = 0\r
+\r
+; **** I2C/TWI ****\r
+; **** I2CR ****\r
+.equ I2INT = 7 \r
+.equ I2EA = 6\r
+.equ I2STA = 5\r
+.equ I2STO = 4\r
+.equ I2WC = 3\r
+.equ ENI2C = 2\r
+.equ I2EN = 2\r
+.equ I2C_TST = 1 ; Present in core test mode only. Write Only.\r
+.equ I2IE = 0\r
+\r
+; **** I2SR ****\r
+.equ I2S7 = 7 \r
+.equ I2S6 = 6\r
+.equ I2S5 = 5\r
+.equ I2S4 = 4\r
+.equ I2S3 = 3\r
+.equ I2GCE = 0 \r
+ \r
+; **** I2AR ****\r
+.equ TWINT = 7\r
+.equ TWEA = 6\r
+.equ TWSTA = 5\r
+.equ TWSTO = 4\r
+.equ TWWC = 3\r
+.equ TWEN = 2\r
+.equ TWC_TST = 1 ; Present in core test mode only. Write Only.\r
+.equ TWIE = 0\r
+\r
+; **** TWSR ****\r
+.equ TWS7 = 7 \r
+.equ TWS6 = 6\r
+.equ TWS5 = 5\r
+.equ TWS4 = 4\r
+.equ TWS3 = 3\r
+.equ TWPS1 = 1\r
+.equ TWPS0 = 0\r
+\r
+; **** TWAR ****\r
+.equ TWA6 = 7\r
+.equ TWA5 = 6\r
+.equ TWA4 = 5\r
+.equ TWA3 = 4\r
+.equ TWA2 = 3\r
+.equ TWA1 = 2\r
+.equ TWA0 = 1\r
+.equ TWGCE = 0\r
+\r
+; **** PORT A ****\r
+; **** PORTA ****\r
+.equ PA7 = 7 \r
+.equ PA6 = 6\r
+.equ PA5 = 5\r
+.equ PA4 = 4\r
+.equ PA3 = 3\r
+.equ PA2 = 2\r
+.equ PA1 = 1\r
+.equ PA0 = 0\r
+.equ PORTA7 = 7\r
+.equ PORTA6 = 6\r
+.equ PORTA5 = 5\r
+.equ PORTA4 = 4\r
+.equ PORTA3 = 3\r
+.equ PORTA2 = 2\r
+.equ PORTA1 = 1\r
+.equ PORTA0 = 0\r
+\r
+; **** DDRA ****\r
+.equ DDA7 = 7 \r
+.equ DDA6 = 6\r
+.equ DDA5 = 5\r
+.equ DDA4 = 4\r
+.equ DDA3 = 3\r
+.equ DDA2 = 2\r
+.equ DDA1 = 1\r
+.equ DDA0 = 0\r
+\r
+; **** PINA ****\r
+.equ PINA7 = 7 \r
+.equ PINA6 = 6\r
+.equ PINA5 = 5\r
+.equ PINA4 = 4\r
+.equ PINA3 = 3\r
+.equ PINA2 = 2\r
+.equ PINA1 = 1\r
+.equ PINA0 = 0\r
+\r
+; **** PORT B ****\r
+; **** PORTB ****\r
+.equ PB7 = 7 \r
+.equ PB6 = 6\r
+.equ PB5 = 5\r
+.equ PB4 = 4\r
+.equ PB3 = 3\r
+.equ PB2 = 2\r
+.equ PB1 = 1\r
+.equ PB0 = 0\r
+.equ PORTB7 = 7\r
+.equ PORTB6 = 6\r
+.equ PORTB5 = 5\r
+.equ PORTB4 = 4\r
+.equ PORTB3 = 3\r
+.equ PORTB2 = 2\r
+.equ PORTB1 = 1\r
+.equ PORTB0 = 0\r
+\r
+; **** DDRB ****\r
+.equ DDB7 = 7 \r
+.equ DDB6 = 6\r
+.equ DDB5 = 5\r
+.equ DDB4 = 4\r
+.equ DDB3 = 3\r
+.equ DDB2 = 2\r
+.equ DDB1 = 1\r
+.equ DDB0 = 0\r
+\r
+; **** PINB ****\r
+.equ PINB7 = 7 \r
+.equ PINB6 = 6\r
+.equ PINB5 = 5\r
+.equ PINB4 = 4\r
+.equ PINB3 = 3\r
+.equ PINB2 = 2\r
+.equ PINB1 = 1\r
+.equ PINB0 = 0\r
+\r
+;**** PORTC ****\r
+.equ PC7 = 7 \r
+.equ PC6 = 6\r
+.equ PC5 = 5\r
+.equ PC4 = 4\r
+.equ PC3 = 3\r
+.equ PC2 = 2\r
+.equ PC1 = 1\r
+.equ PC0 = 0\r
+.equ PORTC7 = 7\r
+.equ PORTC6 = 6\r
+.equ PORTC5 = 5\r
+.equ PORTC4 = 4\r
+.equ PORTC3 = 3\r
+.equ PORTC2 = 2\r
+.equ PORTC1 = 1\r
+.equ PORTC0 = 0\r
+\r
+; **** DDRC ****\r
+.equ DDC7 = 7 \r
+.equ DDC6 = 6\r
+.equ DDC5 = 5\r
+.equ DDC4 = 4\r
+.equ DDC3 = 3\r
+.equ DDC2 = 2\r
+.equ DDC1 = 1\r
+.equ DDC0 = 0\r
+\r
+; **** PINC ****\r
+.equ PINC7 = 7 \r
+.equ PINC6 = 6\r
+.equ PINC5 = 5\r
+.equ PINC4 = 4\r
+.equ PINC3 = 3\r
+.equ PINC2 = 2\r
+.equ PINC1 = 1\r
+.equ PINC0 = 0\r
+\r
+;**** PORTD ****\r
+.equ PD7 = 7 \r
+.equ PD6 = 6\r
+.equ PD5 = 5\r
+.equ PD4 = 4\r
+.equ PD3 = 3\r
+.equ PD2 = 2\r
+.equ PD1 = 1\r
+.equ PD0 = 0\r
+.equ PORTD7 = 7\r
+.equ PORTD6 = 6\r
+.equ PORTD5 = 5\r
+.equ PORTD4 = 4\r
+.equ PORTD3 = 3\r
+.equ PORTD2 = 2\r
+.equ PORTD1 = 1\r
+.equ PORTD0 = 0\r
+\r
+; **** DDRD ****\r
+.equ DDD7 = 7 \r
+.equ DDD6 = 6\r
+.equ DDD5 = 5\r
+.equ DDD4 = 4\r
+.equ DDD3 = 3\r
+.equ DDD2 = 2\r
+.equ DDD1 = 1\r
+.equ DDD0 = 0\r
+\r
+; **** PIND ****\r
+.equ PIND7 = 7 \r
+.equ PIND6 = 6\r
+.equ PIND5 = 5\r
+.equ PIND4 = 4\r
+.equ PIND3 = 3\r
+.equ PIND2 = 2\r
+.equ PIND1 = 1\r
+.equ PIND0 = 0\r
+\r
+;**** PORTE ****\r
+.equ PE7 = 7\r
+.equ PE6 = 6\r
+.equ PE5 = 5\r
+.equ PE4 = 4\r
+.equ PE3 = 3\r
+.equ PE2 = 2\r
+.equ PE1 = 1\r
+.equ PE0 = 0\r
+.equ PORTE7 = 7\r
+.equ PORTE6 = 6\r
+.equ PORTE5 = 5\r
+.equ PORTE4 = 4\r
+.equ PORTE3 = 3\r
+.equ PORTE2 = 2\r
+.equ PORTE1 = 1\r
+.equ PORTE0 = 0\r
+\r
+; **** DDRE ****\r
+.equ DDE7 = 7 \r
+.equ DDE6 = 6\r
+.equ DDE5 = 5\r
+.equ DDE4 = 4\r
+.equ DDE3 = 3\r
+.equ DDE2 = 2\r
+.equ DDE1 = 1\r
+.equ DDE0 = 0\r
+\r
+; **** PINE ****\r
+.equ PINE7 = 7 \r
+.equ PINE6 = 6\r
+.equ PINE5 = 5\r
+.equ PINE4 = 4\r
+.equ PINE3 = 3\r
+.equ PINE2 = 2\r
+.equ PINE1 = 1\r
+.equ PINE0 = 0\r
+\r
+; **** PORTF ****\r
+.equ PF7 = 7 \r
+.equ PF6 = 6\r
+.equ PF5 = 5\r
+.equ PF4 = 4\r
+.equ PF3 = 3\r
+.equ PF2 = 2\r
+.equ PF1 = 1\r
+.equ PF0 = 0\r
+.equ PORTF7 = 7\r
+.equ PORTF6 = 6\r
+.equ PORTF5 = 5\r
+.equ PORTF4 = 4\r
+.equ PORTF3 = 3\r
+.equ PORTF2 = 2\r
+.equ PORTF1 = 1\r
+.equ PORTF0 = 0\r
+\r
+; **** DDRF ****\r
+.equ DDF7 = 7 \r
+.equ DDF6 = 6\r
+.equ DDF5 = 5\r
+.equ DDF4 = 4\r
+.equ DDF3 = 3\r
+.equ DDF2 = 2\r
+.equ DDF1 = 1\r
+.equ DDF0 = 0\r
+\r
+; **** PINF ****\r
+.equ PINF7 = 7 \r
+.equ PINF6 = 6\r
+.equ PINF5 = 5\r
+.equ PINF4 = 4\r
+.equ PINF3 = 3\r
+.equ PINF2 = 2\r
+.equ PINF1 = 1\r
+.equ PINF0 = 0\r
+\r
+; **** PORTG ****\r
+.equ PG4 = 4 \r
+.equ PG3 = 3\r
+.equ PG2 = 2 \r
+.equ PG1 = 1\r
+.equ PG0 = 0\r
+\r
+; **** DDRG ****\r
+.equ DDG4 = 4 \r
+.equ DDG3 = 3\r
+.equ DDG2 = 2\r
+.equ DDG1 = 1\r
+.equ DDG0 = 0\r
+\r
+; **** PING ****\r
+.equ PING4 = 4\r
+.equ PING3 = 3 \r
+.equ PING2 = 2\r
+.equ PING1 = 1\r
+.equ PING0 = 0\r
+\r
+\r
+;*****************************************************************************\r
+; CPU Register Declarations\r
+;*****************************************************************************\r
+\r
+.def XL = r26 ; X pointer low\r
+.def XH = r27 ; X pointer high\r
+.def YL = r28 ; Y pointer low\r
+.def YH = r29 ; Y pointer high\r
+.def ZL = r30 ; Z pointer low\r
+.def ZH = r31 ; Z pointer high\r
+\r
+\r
+;*****************************************************************************\r
+; Data Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ RAMEND = $10ff ; Highest internal data memory (SRAM) address.\r
+.equ EEPROMEND = $07ff ; Highest EEPROM address.\r
+ \r
+;*****************************************************************************\r
+; Program Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ FLASHEND = $7FFF ; Highest program memory (flash) address\r
+ ; (When addressed as 16 bit words)\r
+ \r
+;**** Boot Vectors ****\r
+ ; byte groups\r
+ ; /--\/--\/--\/--\ \r
+.equ SMALLBOOTSTART = 0b0111111000000000 ; ($7E00) Smallest boot block is 512W\r
+.equ SECONDBOOTSTART = 0b0111110000000000 ; ($7C00) 2'nd boot block size is 1KW\r
+.equ THIRDBOOTSTART = 0b0111100000000000 ; ($7800) Third boot block size is 2KW\r
+.equ LARGEBOOTSTART = 0b0111000000000000 ; ($7000) Largest boot block is 4KW\r
+\r
+\r
+;**** Page Size ****\r
+.equ PAGESIZE = 128 ; Number of WORDS in a page\r
+\r
+\r
+;**** Interrupt Vectors ****\r
+.equ INT0addr = $002 ; External Interrupt0 Vector Address\r
+.equ INT1addr = $004 ; External Interrupt1 Vector Address\r
+.equ INT2addr = $006 ; External Interrupt2 Vector Address\r
+.equ INT3addr = $008 ; External Interrupt3 Vector Address\r
+.equ INT4addr = $00a ; External Interrupt4 Vector Address\r
+.equ INT5addr = $00c ; External Interrupt5 Vector Address\r
+.equ INT6addr = $00e ; External Interrupt6 Vector Address\r
+.equ INT7addr = $010 ; External Interrupt7 Vector Address\r
+.equ OC2addr = $012 ; Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr = $014 ; Overflow2 Interrupt Vector Address\r
+.equ ICP1addr = $016 ; Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr = $018 ; Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr = $01a ; Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr = $01c ; Overflow1 Interrupt Vector Address\r
+.equ OC0addr = $01e ; Output Compare0 Interrupt Vector Address\r
+.equ OVF0addr = $020 ; Overflow0 Interrupt Vector Address\r
+.equ SPIaddr = $022 ; SPI Interrupt Vector Address\r
+.equ URXC0addr = $024 ; USART0 Receive Complete Interrupt Vector Address\r
+.equ UDRE0addr = $026 ; USART0 Data Register Empty Interrupt Vector Address\r
+.equ UTXC0addr = $028 ; USART0 Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr = $02a ; ADC Conversion Complete Handle\r
+.equ ERDYaddr = $02c ; EEPROM Write Complete Handle\r
+.equ ACIaddr = $02e ; Analog Comparator Interrupt Vector Address\r
+\r
+.equ OC1Caddr = $030 ; Output Compare1C Interrupt Vector Address\r
+.equ ICP3addr = $032 ; Input Capture3 Interrupt Vector Address\r
+.equ OC3Aaddr = $034 ; Output Compare3A Interrupt Vector Address\r
+.equ OC3Baddr = $036 ; Output Compare3B Interrupt Vector Address\r
+.equ OC3Caddr = $038 ; Output Compare3C Interrupt Vector Address\r
+.equ OVF3addr = $03A ; Overflow3 Interrupt Vector Address\r
+.equ URXC1addr = $03C ; USART1 Receive Complete Interrupt Vector Address\r
+.equ UDRE1addr = $03E ; USART1 Data Register Empty Interrupt Vector Address\r
+.equ UTXC1addr = $040 ; USART1 Transmit Complete Interrupt Vector Address\r
+.equ I2Caddr = $042 ; I2C Interrupt Vector Address\r
+.equ TWIaddr = $042 ; TWI Interrupt Vector Address\r
+.equ SPMRaddr = $044 ; Store Program Memory Ready Interrupt Vector Address\r
+\r
+\r
+;**** End of File ****\r
projects / my-code / atmel.git / blobdiff