--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m162def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega162\r
+;* Date :2001.09.19\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega162\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega162\r
+ \r
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****\r
+;**** Not available in Mega162 compatibility mode ****\r
+.equ TCCR3A =$8b\r
+.equ TCCR3B =$8a \r
+.equ TCNT3H =$89\r
+.equ TCNT3L =$88\r
+.equ OCR3AH =$87\r
+.equ OCR3AL =$86 \r
+.equ OCR3BH =$85\r
+.equ OCR3BL =$84\r
+.equ ICR3H =$81\r
+.equ ICR3L =$80\r
+.equ ETIMSK =$7d\r
+.equ ETIFR =$7c\r
+.equ PCMSK1 =$6c\r
+.equ PCMSK0 =$6b\r
+.equ CLKPR =$61 \r
+ \r
+;***** I/O Register Definitions \r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ UCSR1C =$3c ; Note! UCSR1C equals UBRR1H\r
+.equ UBRR1H =$3c ; Note! UCSR1C equals UBRR1H\r
+.equ EIMSK =$3b \r
+.equ GIMSK =$3b\r
+.equ GICR =$3b ; new name for GIMSK\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ EMCUCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ; For compatibility, \r
+.equ MCUCSR =$34 ; keep both names until further \r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OCR0 =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ TCCR2 =$27\r
+.equ ASSR =$26\r
+.equ ICR1H =$25\r
+.equ ICR1L =$24\r
+.equ TCNT2 =$23\r
+.equ OCR2 =$22\r
+.equ WDTCR =$21\r
+.equ UBRRHI =$20 ; Old ATmega161\r
+.equ UCSR0C =$20 ; Note! UCSR0C equals UBRR0H\r
+.equ UBRR0H =$20 ; Note! UCSR0C equals UBRR0H \r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR0 =$0c\r
+.equ UDR =$0c ;for compatibility with s8515\r
+.equ UCSR0A =$0b\r
+.equ USR =$0b ;for compatibility with s8515\r
+.equ UCSR0B =$0a\r
+.equ UCR =$0a ;for compatibility with s8515\r
+.equ UBRR0 =$09 ;Old mega161\r
+.equ UBRR0L =$09 \r
+.equ UBRR =$09 ;for compatibility with s8515\r
+.equ ACSR =$08\r
+.equ PORTE =$07\r
+.equ DDRE =$06\r
+.equ PINE =$05\r
+.equ OSCCAL =$04 ; New\r
+.equ UDR1 =$03\r
+.equ UCSR1A =$02\r
+.equ UCSR1B =$01\r
+.equ UBRR1 =$00 ;Old mega161\r
+.equ UBRR1L =$00\r
+\r
+;***** Bit Definitions\r
+;TCCR3A\r
+.equ COM3A1 =7\r
+.equ COM3A0 =6\r
+.equ COM3B1 =5\r
+.equ COM3B0 =4\r
+.equ FOC3A =3\r
+.equ FOC3B =2\r
+.equ WGM31 =1\r
+.equ WGM30 =0\r
+\r
+;TCCR3A\r
+.equ ICNC3 =7\r
+.equ ICES3 =6\r
+.equ WGM33 =4\r
+.equ WGM32 =3\r
+.equ CS32 =2\r
+.equ CS31 =1\r
+.equ CS30 =0\r
+\r
+;ETIMSK\r
+.equ TICIE3 =5\r
+.equ OCIE3A =4\r
+.equ OCIE3B =3\r
+.equ TOIE3 =2\r
+ \r
+;ETIFR\r
+.equ ICF3 =5\r
+.equ OCF3A =4\r
+.equ OCF3B =3\r
+.equ TOV3 =2\r
+\r
+;PCMSK1\r
+.equ PCINT15 =7\r
+.equ PCINT14 =6\r
+.equ PCINT13 =5\r
+.equ PCINT12 =4 \r
+.equ PCINT11 =3\r
+.equ PCINT10 =2 \r
+.equ PCINT9 =1\r
+.equ PCINT8 =0\r
+ \r
+;PCMSK1\r
+.equ PCINT7 =7\r
+.equ PCINT6 =6\r
+.equ PCINT5 =5\r
+.equ PCINT4 =4 \r
+.equ PCINT3 =3\r
+.equ PCINT2 =2 \r
+.equ PCINT1 =1\r
+.equ PCINT0 =0\r
+\r
+;CLKPR\r
+.equ CLKPCE =7\r
+.equ CLKPS3 =3\r
+.equ CLKPS2 =2 \r
+.equ CLKPS1 =1\r
+.equ CLKPS0 =0\r
+ \r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+.equ PCIE1 =4\r
+.equ PCIE0 =3 \r
+.equ IVSEL =1 ; Interrupt vector select\r
+.equ IVCE =0 ; Interrupt vector change enable\r
+ \r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+.equ PCIF1 =4\r
+.equ PCIF0 =3 \r
+ \r
+ \r
+;TIMSK\r
+.equ TOIE1 =7\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ OCIE2 =4\r
+.equ TICIE1 =3\r
+.equ TOIE2 =2\r
+.equ TOIE0 =1\r
+.equ OCIE0 =0\r
+\r
+;TIFR\r
+.equ TOV1 =7\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ OCF2 =4\r
+.equ ICF1 =3\r
+.equ TOV2 =2\r
+.equ TOV0 =1\r
+.equ OCF0 =0\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ RWWSB =6\r
+.equ ASB =6 ; old\r
+.equ RWWSRE =4\r
+.equ ASRE =4 ; old\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;EMCUCR\r
+.equ SM0 =7\r
+.equ SRL2 =6\r
+.equ SRL1 =5\r
+.equ SRL0 =4\r
+.equ SRW01 =3\r
+.equ SRW00 =2\r
+.equ SRW11 =1\r
+.equ ISC2 =0\r
+\r
+;MCUCR\r
+.equ SRE =7\r
+.equ SRW =6 ;for compatibility with s8515\r
+.equ SRW10 =6\r
+.equ SE =5\r
+.equ SM =4 ;for compatibility with s8515\r
+.equ SM1 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUSR\r
+.equ JTD =7 \r
+.equ SM2 =5 \r
+.equ JTRF =4 \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ WGM00 =6\r
+.equ PWM0 =6 ; OBSOLETE! Use WGM00\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ WGM01 =3\r
+.equ CTC0 =3 ; OBSOLETE! Use WGM01\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;SFIOR\r
+.equ TSM = 7\r
+.equ XMBK = 6 ; Added for Mega162\r
+.equ XMM2 = 5\r
+.equ XMM1 = 4\r
+.equ XMM0 = 3\r
+.equ PUD = 2\r
+.equ PSR2 = 1\r
+.equ PSR10 = 0 ; Note: The prescaler reset is shared\r
+ ; between timer 0 and 1.\r
+.equ PSR1 = 0\r
+.equ PSR0 = 0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1 ; OBSOLETE! Use WGM11\r
+.equ WGM11 =1\r
+.equ PWM10 =0 ; OBSOLETE! Use WGM10\r
+.equ WGM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC11 =4 ; OBSOLETE! Use WGM13\r
+.equ WGM13 =4\r
+.equ CTC10 =3 ; OBSOLETE! Use WGM12\r
+.equ WGM12 =3\r
+.equ CTC1 =3 ; Old Mega161\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ WGM20 =6\r
+.equ PWM2 =6 ; OBSOLETE! Use WGM20\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ WGM21 =3\r
+.equ CTC2 =3 ; OBSOLETE! Use WGM21\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDCE =4 ; Added for Mega161B\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PORTA7 =7\r
+.equ PORTA6 =6\r
+.equ PORTA5 =5\r
+.equ PORTA4 =4\r
+.equ PORTA3 =3\r
+.equ PORTA2 =2\r
+.equ PORTA1 =1\r
+.equ PORTA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PORTB7 =7\r
+.equ PORTB6 =6\r
+.equ PORTB5 =5\r
+.equ PORTB4 =4\r
+.equ PORTB3 =3\r
+.equ PORTB2 =2\r
+.equ PORTB1 =1\r
+.equ PORTB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PORTC7 =7\r
+.equ PORTC6 =6\r
+.equ PORTC5 =5\r
+.equ PORTC4 =4\r
+.equ PORTC3 =3\r
+.equ PORTC2 =2\r
+.equ PORTC1 =1\r
+.equ PORTC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PORTD7 =7\r
+.equ PORTD6 =6\r
+.equ PORTD5 =5\r
+.equ PORTD4 =4\r
+.equ PORTD3 =3\r
+.equ PORTD2 =2\r
+.equ PORTD1 =1\r
+.equ PORTD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;PORTE\r
+.equ PORTE2 =2\r
+.equ PORTE1 =1\r
+.equ PORTE0 =0\r
+\r
+;DDRE\r
+.equ DDE2 =2\r
+.equ DDE1 =1\r
+.equ DDE0 =0\r
+\r
+;PINE\r
+.equ PINE2 =2\r
+.equ PINE1 =1\r
+.equ PINE0 =0\r
+\r
+;USR (for compatibility with s8515)\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ U2X =1\r
+\r
+;UCSR0A\r
+.equ RXC0 =7\r
+.equ TXC0 =6\r
+.equ UDRE0 =5\r
+.equ FE0 =4\r
+.equ OR0 =3 ; Old name kept for compatibilty\r
+.equ DOR0 =3\r
+.equ PE0 =2 ; New\r
+.equ U2X0 =1\r
+.equ MPCM0 =0\r
+\r
+;UCSR1A\r
+.equ RXC1 =7\r
+.equ TXC1 =6\r
+.equ UDRE1 =5\r
+.equ FE1 =4\r
+.equ OR1 =3 ; Old name kept for compatibilty\r
+.equ DOR1 =3\r
+.equ PE1 =2 ; New\r
+.equ U2X1 =1\r
+.equ MPCM1 =0\r
+\r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;UCR (for compatibility with s8515)\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; Old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+; UCSR0B\r
+.equ RXCIE0 =7\r
+.equ TXCIE0 =6\r
+.equ UDRIE0 =5\r
+.equ RXEN0 =4\r
+.equ TXEN0 =3\r
+.equ CHR90 =2 ; Old name kept for compatibilty\r
+.equ UCSZ02 =2\r
+.equ RXB80 =1\r
+.equ TXB80 =0\r
+\r
+; UCSR1B\r
+.equ RXCIE1 =7\r
+.equ TXCIE1 =6\r
+.equ UDRIE1 =5\r
+.equ RXEN1 =4\r
+.equ TXEN1 =3\r
+.equ CHR91 =2 ; Old name kept for compatibilty\r
+.equ UCSZ12 =2\r
+.equ RXB81 =1\r
+.equ TXB81 =0\r
+ \r
+;UCSR0C New \r
+.equ URSEL0 =7\r
+.equ UMSEL0 =6\r
+.equ UPM01 =5\r
+.equ UPM00 =4\r
+.equ USBS0 =3\r
+.equ UCSZ01 =2\r
+.equ UCSZ00 =1\r
+.equ UCPOL0 =0\r
+\r
+;UCSR1C New \r
+.equ URSEL1 =7\r
+.equ UMSEL1 =6\r
+.equ UPM11 =5\r
+.equ UPM10 =4\r
+.equ USBS1 =3\r
+.equ UCSZ11 =2\r
+.equ UCSZ10 =1\r
+.equ UCPOL1 =0\r
+ \r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ AINBG =6 ; Old mega161\r
+.equ ACBG =6 \r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+\r
+\r
+; Boot loader Lock bit\r
+.equ BLB12 =5\r
+.equ BLB11 =4\r
+.equ BLB02 =3\r
+.equ BLB01 =2\r
+\r
+;*****************************************************************************\r
+; CPU Register Declarations\r
+;*****************************************************************************\r
+\r
+.def XL = r26 ; X pointer low\r
+.def XH = r27 ; X pointer high\r
+.def YL = r28 ; Y pointer low\r
+.def YH = r29 ; Y pointer high\r
+.def ZL = r30 ; Z pointer low\r
+.def ZH = r31 ; Z pointer high\r
+\r
+\r
+;*****************************************************************************\r
+; Data Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ RAMEND = $488 ; Highest internal data memory (SRAM) address.\r
+ ;(1k RAM + IO + REG)\r
+.equ EEPROMEND = $01ff ; Highest EEPROM address.\r
+ ;(512 byte)\r
+;*****************************************************************************\r
+; Program Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ FLASHEND = $1FFF ; Highest program memory (flash) address\r
+ ; (When addressed as 16 bit words)\r
+ ; ( 8k words , 16k byte ) \r
+ \r
+;**** Boot Vectors ****\r
+ ; byte groups\r
+ ; /--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B\r
+.equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B\r
+.equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB\r
+.equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+\r
+\r
+\r
+\r
+.equ INT0addr = $002 ; External Interrupt Request 0\r
+.equ INT1addr = $004 ; External Interrupt Request 1\r
+.equ INT2addr = $006 ; External Interrupt Request 2\r
+.equ PCINT0addr = $008 ; Pin Change Interrupt Request 0\r
+.equ PCINT1addr = $00A\r
+.equ TIMER3CAPTaddr = $00C\r
+.equ TIMER3COMPAaddr = $00E\r
+.equ TIMER3COMPBaddr = $010\r
+.equ TIMER3OVFaddr = $012\r
+.equ TIMER2COMPaddr = $014\r
+.equ TIMER2OVFaddr = $016\r
+.equ TIMER1CAPTaddr = $018\r
+.equ TIMER1COMPAaddr = $01A\r
+.equ TIMER1COMPBaddr = $01C\r
+.equ TIMER1OVFaddr = $01E\r
+.equ TIMER0COMPaddr = $020\r
+.equ TIMER0OVFaddr = $022\r
+.equ SPISTCaddr = $024\r
+.equ USART0RXCaddr = $026\r
+.equ USART1RXCaddr = $028\r
+.equ USART0UDREaddr = $02A\r
+.equ USART1UDREaddr = $02C\r
+.equ USART0TXCaddr = $02E\r
+.equ USART1TXCaddr = $030\r
+.equ EE_RDYaddr = $032\r
+.equ ANA_CMPaddr = $034\r
+.equ SPM_RDYaddr = $036\r
projects / my-code / atmel.git / blobdiff