--- /dev/null
+;****************************************************************************************\r
+;* This can be included in the assembly file\r
+;* in order to use the names in the spec sheet.\r
+;* \r
+;* I/O Register Definitions per AT86RF401 spec\r
+;****************************************************************************************\r
+\r
+;***** device directive, will make the assembler check for illegal instructions.\r
+.device AT86RF401\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3F ; Status \r
+.equ SPH =$3E ; Stack Pointer High \r
+.equ SPL =$3D ; Stack Pointer Low \r
+.equ BL_CONFIG =$35 ; Battery Low Configuration \r
+.equ B_DET =$34 ; Button Detect \r
+.equ PWR_CTL =$33 ; Power Control \r
+.equ IO_DATIN =$32 ; I/O Data In \r
+.equ IO_DATOUT =$31 ; I/O Data Out \r
+.equ IO_ENAB =$30 ; I/O Enable\r
+.equ WDTCR =$22 ; Watchdog Timer Control\r
+.equ BTCR =$21 ; Bit Timer Control\r
+.equ BTCNT =$20 ; Bit Timer Count\r
+.equ DEEAR =$1E ; Data EEPROM Address\r
+.equ DEEDR =$1D ; Data EEPROM Data\r
+.equ DEECR =$1C ; Data EEPROM Control\r
+.equ LOCKDET2 =$17 ; Lock Detector Configuration Register 2\r
+.equ VCOTUNE =$16 ; VCO Tuning Register\r
+.equ PWR_ATTEN =$14 ; Power Attenuation Control Register\r
+.equ TX_CNTL =$12 ; Transmitter Control Register\r
+.equ LOCKDET1 =$10 ; Lock Detector Configuration Register 1\r
+.equ SRAM_START =$0060 ; Start of RAM\r
+.equ SRAM_END =$00DF ; End of RAM\r
+\r
+;**** Bit Definitions\r
+; SREG\r
+.equ I =7\r
+.equ T =6\r
+.equ H =5\r
+.equ S =4\r
+.equ V =3\r
+.equ N =2\r
+.equ Z =1\r
+.equ C =0\r
+\r
+; BL_CONFIG\r
+.equ BL =7\r
+.equ BLV =6\r
+.equ BL5 =5\r
+.equ BL4 =4\r
+.equ BL3 =3\r
+.equ BL2 =2\r
+.equ BL1 =1\r
+.equ BL0 =0\r
+\r
+; B_DET\r
+.equ BD5 =5\r
+.equ BD4 =4\r
+.equ BD3 =3\r
+.equ BD2 =2\r
+.equ BD1 =1\r
+.equ BD0 =0\r
+\r
+; PWR_CTL\r
+.equ ACS2 =7\r
+.equ ACS1 =6\r
+.equ ACS0 =5\r
+.equ TM =4\r
+.equ BD =3\r
+.equ BLI =2\r
+.equ SLEEP =1\r
+.equ BBM =0\r
+\r
+; IO_DATIN\r
+.equ IOI5 =5\r
+.equ IOI4 =4\r
+.equ IOI3 =3\r
+.equ IOI2 =2\r
+.equ IOI1 =1\r
+.equ IOI0 =0\r
+\r
+; IO_DATOUT\r
+.equ IOO5 =5\r
+.equ IOO4 =4\r
+.equ IOO3 =3\r
+.equ IOO2 =2\r
+.equ IOO1 =1\r
+.equ IOO0 =0\r
+\r
+; IO_ENAB\r
+.equ BOHYST =6\r
+.equ IOE5 =5\r
+.equ IOE4 =4\r
+.equ IOE3 =3\r
+.equ IOE2 =2\r
+.equ IOE1 =1\r
+.equ IOE0 =0\r
+\r
+; WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+; BTCR\r
+.equ C9 =7\r
+.equ C8 =6\r
+.equ M1 =5\r
+.equ M0 =4\r
+.equ IE =3\r
+.equ F2 =2\r
+.equ DATA =1\r
+.equ F0 =0\r
+\r
+; BTCNT\r
+.equ C7 =7\r
+.equ C6 =6\r
+.equ C5 =5\r
+.equ C4 =4\r
+.equ C3 =3\r
+.equ C2 =2\r
+.equ C1 =1\r
+.equ C0 =0\r
+\r
+; DEEAR\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+; DEEDR\r
+.equ ED7 =7\r
+.equ ED6 =6\r
+.equ ED5 =5\r
+.equ ED4 =4\r
+.equ ED3 =3\r
+.equ ED2 =2\r
+.equ ED1 =1\r
+.equ ED0 =0\r
+\r
+; DEECR\r
+.equ BSY =3\r
+.equ EEU =2\r
+.equ EEL =1\r
+.equ EER =0\r
+\r
+; LOCKDET2\r
+.equ EUD =7\r
+.equ LAT =6\r
+.equ ULC2 =5\r
+.equ ULC1 =4\r
+.equ ULC0 =3\r
+.equ LC2 =2\r
+.equ LC1 =1\r
+.equ LC0 =0\r
+\r
+; VCOTUNE\r
+.equ VCOVDET1 =7\r
+.equ VCOVDET0 =6\r
+.equ VCOTUNE4 =4\r
+.equ VCOTUNE3 =3\r
+.equ VCOTUNE2 =2\r
+.equ VCOTUNE1 =1\r
+.equ VCOTUNE0 =0\r
+\r
+; PWR_ATTEN\r
+.equ PCC2 =5\r
+.equ PCC1 =4\r
+.equ PCC0 =3\r
+.equ PCF2 =2\r
+.equ PCF1 =1\r
+.equ PCF0 =0\r
+\r
+; TX_CNTL\r
+.equ FSK =6\r
+.equ TXE =5\r
+.equ TXK =4\r
+.equ LOC =2\r
+\r
+; LOCKDET1\r
+.equ UPOK =4\r
+.equ ENKO =3\r
+.equ BOD =2\r
+.equ CS1 =1\r
+.equ CS0 =0\r
+\r
+;****************************************************************************************\r
+;* Define global registers\r
+;****************************************************************************************\r
+\r
+.def XL =R26 \r
+.def XH =R27 \r
+.def YL =R28 \r
+.def YH =R29 \r
+.def ZL =R30 \r
+.def ZH =R31 \r
projects / my-code / atmel.git / blobdiff