X-Git-Url: https://www.hackdaworld.org/gitweb/?a=blobdiff_plain;f=monolyzer%2Fmain.asm;h=bcc6c1c87b1ced5d2b0adff680ac0d58cbe830fe;hb=1117f788c441bc3d8caf90e5fb883e11696e1757;hp=97b4d956c597e4663565bc24396e94dc862d1b48;hpb=41d981471644f11151e4f1691c4a29c44fb12410;p=my-code%2Fatmel.git

diff --git a/monolyzer/main.asm b/monolyzer/main.asm
index 97b4d95..bcc6c1c 100644
--- a/monolyzer/main.asm
+++ b/monolyzer/main.asm
@@ -13,6 +13,7 @@
 .def	tmp2		= r17
 .def	uart_rxtx	= r18
 .def	count		= r19
+.def	state		= r20
 
 ;
 ; interrupts
@@ -22,7 +23,7 @@
 rjmp INIT
 
 ; INT0
-reti
+rjmp INT0_IR
 
 ; INT1
 reti
@@ -37,10 +38,10 @@ reti
 reti
 
 ; T0 OVF0
-rjmp T0_OVF
+reti
 
 ; UART RX
-rjmp UART_RECEIVE
+reti
 
 ; UART UDRE
 reti
@@ -85,18 +86,12 @@ INIT:
 	; gio port init
 	rcall PORT_INIT
 
-	; timer0 init
-	rcall TIMER0_INIT
-
-	; timer0 interrupt enable
-	rcall TIMER0_INT_INIT
+	; timer1 init
+	rcall TIMER1_INIT
 
 	; uart init
 	rcall UART_INIT
 
-	; uart interrupt enable
-	rcall UART_INT_RX_INIT
-
 	; zero and one initialization
 	ldi tmp1,0
 	mov zero,tmp1
@@ -108,49 +103,114 @@ INIT:
 	out SPL,tmp1
 
 	; more init
-	ldi count,0x21
+	ldi count,0
+	ldi state,1
+
+	; storage pointer
+	ldi ZL,low(STORAGE)
+	ldi ZH,high(STORAGE)
+
+	; counter
+	ldi tmp1,0
+	out TCNT1H,tmp1
+	out TCNT1L,tmp1
 
 	; signal ready output
-	ldi uart_rxtx,0x68
+	ldi uart_rxtx,0x72
 	rcall UART_TX
 
+	; external interrupt enable
+	rcall INT0_IR_CONF
+	rcall INT0_IR_ENABLE
+
 	; global interrupt enable
 	sei 
 
 MAIN:
 
-WAIT_FOR_HIGH:
-	; start as soon as we get a high signal
+SAMPLE:
+
+	; sample as long as there is storage capacity
+	sbrc state,0
+	rjmp SAMPLE
+
+	; external interrupt enable
+	rcall INT0_IR_DISABLE
+
+	; signal finish
+	ldi uart_rxtx,0x66
+	rcall UART_TX
+
+IDLE:
 
-	rjmp WAIT_FOR_HIGH
+	; wait for commands via uart
+	rcall UART_RX
 
+	; decode instruction
+	cpi uart_rxtx,0x52
+	breq RESET
+	cpi uart_rxtx,0x54
+	breq TRANSFER
+
+	rjmp IDLE
+
+TRANSFER:
+
+	; reset storage pointer
+	ldi ZL,low(STORAGE)
+	ldi ZH,high(STORAGE)
+	ldi count,0
+
+TRANSFER_LOOP:
+
+	; transmit storage
+	ld uart_rxtx,Z+
+	rcall UART_TX
+
+	; count sent data
+	add count,one
+
+	; check amount of sent data
+	cpi count,110
+	breq IDLE
+
+	rjmp TRANSFER_LOOP
 
 ; include subroutines
 .include "port.asm"
 .include "timer.asm"
 .include "uart.asm"
 
-
 ;
 ; interrupt routines
 ;
 
-T0_OVF:
+INT0_IR:
 
 	; debug output
-	cbi PORTD,3
+	; cbi PORTD,3
+
+	; write timer value into sram
+	in tmp1,TCNT1L
+	in tmp2,TCNT1H
+	st Z+,tmp2
+	st Z+,tmp1
 
-	; read port
+	; inc counter
+	add count,one
 
-	; store another byte into sram
+	; check for left capacity
+	cpi count,55
+	brne EXIT_IR
 
+	; exit sampling
+	ldi state,0
+
+EXIT_IR:
 
 	; debug output
-	sbi PORTD,3
-	
-	reti
+	; sbi PORTD,3
 
-UART_RECEIVE:
 	reti
 
 
@@ -160,6 +220,5 @@ UART_RECEIVE:
 
 .dseg
 
-DATA_STORAGE: .byte 8
-
+STORAGE: .byte 110