X-Git-Url: https://www.hackdaworld.org/gitweb/?a=blobdiff_plain;f=monolyzer%2Fmain.asm;h=8795636ee213fef05e12abd34d1b8fd716b77290;hb=f9e6ded1910b07f37d30e24c69ac6c9bf5438178;hp=bcc6c1c87b1ced5d2b0adff680ac0d58cbe830fe;hpb=1117f788c441bc3d8caf90e5fb883e11696e1757;p=my-code%2Fatmel.git

diff --git a/monolyzer/main.asm b/monolyzer/main.asm
index bcc6c1c..8795636 100644
--- a/monolyzer/main.asm
+++ b/monolyzer/main.asm
@@ -14,6 +14,7 @@
 .def	uart_rxtx	= r18
 .def	count		= r19
 .def	state		= r20
+.def	scount		= r21
 
 ;
 ; interrupts
@@ -35,7 +36,7 @@ reti
 reti
 
 ; T1 OVF1
-reti
+rjmp T1_OVF_IR
 
 ; T0 OVF0
 reti
@@ -104,23 +105,41 @@ INIT:
 
 	; more init
 	ldi count,0
-	ldi state,1
+	ldi state,0
 
 	; storage pointer
 	ldi ZL,low(STORAGE)
 	ldi ZH,high(STORAGE)
 
-	; counter
-	ldi tmp1,0
-	out TCNT1H,tmp1
-	out TCNT1L,tmp1
+	ldi scount,0
+	ldi tmp1,0x23
+INIT_STORAGE:
+	; init storage
+	st Z+,tmp1
+	st Z+,tmp1
+	add scount,one
+	cpi scount,55
+	brne INIT_STORAGE
+
+	; storage pointer again
+	ldi ZL,low(STORAGE)
+	ldi ZH,high(STORAGE)
 
 	; signal ready output
 	ldi uart_rxtx,0x72
 	rcall UART_TX
 
+DEBUG_PORT:
+	;rcall UART_RX
+	;ldi uart_rxtx,0x30
+	;in tmp1,PIND
+	;sbrc tmp1,2
+	;ldi uart_rxtx,0x31
+	;rcall UART_TX
+	;rjmp DEBUG_PORT
+
 	; external interrupt enable
-	rcall INT0_IR_CONF
+	rcall INT0_IR_CONF_INIT
 	rcall INT0_IR_ENABLE
 
 	; global interrupt enable
@@ -130,12 +149,13 @@ MAIN:
 
 SAMPLE:
 
-	; sample as long as there is storage capacity
-	sbrc state,0
-	rjmp SAMPLE
+	; sample as long as there is storage capacity and signal
+	cpi state,2
+	brne SAMPLE
 
-	; external interrupt enable
+	; disable interrupts
 	rcall INT0_IR_DISABLE
+	rcall TIMER1_INT_DISABLE
 
 	; signal finish
 	ldi uart_rxtx,0x66
@@ -159,19 +179,25 @@ TRANSFER:
 	; reset storage pointer
 	ldi ZL,low(STORAGE)
 	ldi ZH,high(STORAGE)
-	ldi count,0
+	ldi scount,1
+
+	; transmit number of sampled words
+	mov uart_rxtx,count
+	rcall UART_TX
 
 TRANSFER_LOOP:
 
-	; transmit storage
+	; send data and counter
+	ld uart_rxtx,Z+
+	rcall UART_TX
 	ld uart_rxtx,Z+
 	rcall UART_TX
 
 	; count sent data
-	add count,one
+	add scount,one
 
-	; check amount of sent data
-	cpi count,110
+	; check amount of data
+	cpi scount,56
 	breq IDLE
 
 	rjmp TRANSFER_LOOP
@@ -190,21 +216,50 @@ INT0_IR:
 	; debug output
 	; cbi PORTD,3
 
-	; write timer value into sram
+	; get timer value
 	in tmp1,TCNT1L
 	in tmp2,TCNT1H
+
+	; check for initial or running state
+	cpi state,0
+	brne INT0_RUN
+
+	; configure interrupt for running state
+	rcall INT0_IR_CONF_RUN
+	ldi state,1
+
+	; reset timer and start ovf interrupt
+	ldi tmp1,0
+	out TCNT1H,tmp1
+	out TCNT1L,tmp1
+	rcall TIMER1_INT_ENABLE
+
+	rjmp EXIT_IR
+
+INT0_RUN:
+
+	; write timer value into sram
 	st Z+,tmp2
 	st Z+,tmp1
 
 	; inc counter
 	add count,one
+	
+	; reset timer
+	ldi tmp1,0
+	out TCNT1H,tmp1
+	out TCNT1L,tmp1
 
 	; check for left capacity
 	cpi count,55
 	brne EXIT_IR
 
+	; indicate end of 'c'apacity
+	ldi uart_rxtx,0x63
+	rcall UART_TX
+
 	; exit sampling
-	ldi state,0
+	ldi state,2
 
 EXIT_IR:
 
@@ -213,6 +268,17 @@ EXIT_IR:
 
 	reti
 
+T1_OVF_IR:
+
+	; indicate 'o'verflow end
+	ldi uart_rxtx,0x6f
+	rcall UART_TX
+
+	; exit sampling
+	ldi state,2
+
+	reti
+
 
 ;
 ; sram