X-Git-Url: https://www.hackdaworld.org/gitweb/?a=blobdiff_plain;f=fx2%2Ffx2.c;h=90e40e9d815b0543b78ff702d607c510a39e644e;hb=377aec2d8eaacb1f970ae36154f36a7f2554b7c7;hp=fcb3dd4c77f8a9596e29d1750a0412cad007a247;hpb=75c2e8a71233f3f55f5fbcc73b4eef7fa93c216c;p=my-code%2Ffpga.git

diff --git a/fx2/fx2.c b/fx2/fx2.c
index fcb3dd4..90e40e9 100644
--- a/fx2/fx2.c
+++ b/fx2/fx2.c
@@ -3,9 +3,9 @@
  *
  * author: hackbard@hackdaworld.org
  *
- * number of priorities:
- * - switch on board power
- * - allow high speed usb transfer
+ * feature list:
+ * - switch on board power (done)
+ * - allow high speed bulk usb transfer
  * - do jtag
  * 
  */
@@ -40,6 +40,8 @@ xdata at 0xe618 volatile u8 EP2FIFOCFG;
 xdata at 0xe619 volatile u8 EP4FIFOCFG;
 xdata at 0xe61a volatile u8 EP6FIFOCFG;
 xdata at 0xe61b volatile u8 EP8FIFOCFG;
+xdata at 0xe620 volatile u8 EP2AUTOINLENH;
+xdata at 0xe621 volatile u8 EP2AUTOINLENL;
 xdata at 0xe624 volatile u8 EP6AUTOINLENH;
 xdata at 0xe625 volatile u8 EP6AUTOINLENL;
 
@@ -55,18 +57,43 @@ sfr at 0xb0 IOD;
 	nop; nop; nop; nop; nop; nop; nop; nop; \
 	nop; _endasm
 
-void power_on() {
+void power_init() {
 
-	/* high level must be applied to the mosfet gate for power on
+	/* pin 7 of port d connected to mosfet gate controlling the board power
 	 *
 	 * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
 	 */
 
 	/* configure pin 7 of port d as output */
 	OED|=(1<<7);
+	SYNCDELAY;
+
+}
+
+void toggle_power() {
+
+	/* toggle high/low state of the mosfet gate */
+
+	if((IOD&(1<<7)))
+		IOD&=~(1<<7);
+	else
+		IOD|=(1<<7);
+
+	SYNCDELAY;
+
+}
+
+void cpu_init() {
+
+	/* cpu initialization: (0x10)
+	 * - 48 mhz
+	 * - none inverted signal
+	 * - no clk out
+	 */
+
+	CPUCS=(1<<4);
+	SYNCDELAY;
 
-	/* pull it high */
-	IOD|=(1<<7);
 }
 
 void slave_fifo_init() {
@@ -76,21 +103,28 @@ void slave_fifo_init() {
 
 	/* set bit 0 and 1 - fifo slave config */	
 	IFCONFIG|=0x03;
+	SYNCDELAY;
 
 	/* async mode */
 	IFCONFIG|=0x04;
+	SYNCDELAY;
 
 	/* p. 180: must be set to 1 */
 	REVCTL|=((1<<0)|(1<<1));
+	SYNCDELAY;
 
 	/* 8 bit fifo to all endpoints
 	 *
 	 * ('or' of all these bits define port d functionality)
 	 */
 	EP2FIFOCFG&=~(1<<0);
+	SYNCDELAY;
 	EP4FIFOCFG&=~(1<<0);
+	SYNCDELAY;
 	EP6FIFOCFG&=~(1<<0);
+	SYNCDELAY;
 	EP8FIFOCFG&=~(1<<0);
+	SYNCDELAY;
 
 	/* default indexed flag configuration:
 	 *
@@ -103,36 +137,49 @@ void slave_fifo_init() {
 
 	/* endpoint configuration:
 	 *
-	 * ep2: bulk in 4x512
-	 * ep6: bulk out 4x512
+	 * ep2: bulk out 4x512
+	 * ep6: bulk in 4x512
 	 *
 	 * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
 	 * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
-	 * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
 	 */
 	EP2CFG=0xa0;
-	EP4CFG=0x01;
+	SYNCDELAY;
+	EP4CFG&=(~0x80);
+	SYNCDELAY;
 	EP6CFG=0xe0;
-	EP8CFG=0x01;
+	SYNCDELAY;
+	EP8CFG&=(~0x80);
+	SYNCDELAY;
 
 	/* reset the fifo */
 	FIFORESET=0x80; /* nak all transfers */
+	SYNCDELAY;
 	FIFORESET=0x02; /* reset ep2 */
+	SYNCDELAY;
 	FIFORESET=0x06; /* reset ep6 */
+	SYNCDELAY;
 	FIFORESET=0x00; /* restore normal operation */
+	SYNCDELAY;
 
 	/* auto in/out, no cpu interaction! auto in len = 512 */
 	EP2FIFOCFG|=(1<<4);
+	SYNCDELAY;
 	EP6FIFOCFG|=(1<<3);
+	SYNCDELAY;
 	EP6AUTOINLENH=(1<<1);
+	SYNCDELAY;
 	EP6AUTOINLENL=0;
+	SYNCDELAY;
 
-	/* maybe OUTPKTEND necessary (with skip=1) */
 }
 
 void ep1_init() {
 
-	/* initialize endpoint 1 (will be used for jtag) */
+	/* initialize endpoint 1
+	 *
+	 * used for jtag & control
+	 */
 
 	/* endpoint 1 configuration:
 	 *
@@ -143,13 +190,18 @@ void ep1_init() {
 
 void fx2_init() {
 
-	/* swicth on power */
-	power_on();
+	/* cpu init */
+	cpu_init();
+
+	/* power init & power on */
+	power_init();
+	toggle_power();
 
 	/* slave fifo init */
 	slave_fifo_init();
 
-	/* ep1_init(); */
+	/* ep1 init */
+	ep1_init();
 }
 
 void main() {