+ SYNCDELAY;
+
+}
+
+void toggle_power() {
+
+ /* toggle high/low state of the mosfet gate */
+
+ if((IOD&(1<<7)))
+ IOD&=~(1<<7);
+ else
+ IOD|=(1<<7);
+
+ SYNCDELAY;
+
+}
+
+void jtag_init() {
+
+ /* pin 5 of port d disables tdi -> tdo forward */
+ OED|=(1<<5);
+ IOD|=(1<<5);
+
+ /* jtag pins:
+ * tdi - pin 0 (input)
+ * tdo - pin 2 (output)
+ * tms - pin 3 (output)
+ * tck - pin 4 (output)
+ */
+ OED|=((1<<2)|(1<<3)|(1<<4));
+ OED&=~(1<<0);
+
+}
+
+void cpu_init() {
+
+ /* cpu initialization: (0x10)
+ * - 48 mhz
+ * - none inverted signal
+ * - no clk out
+ */
+
+ CPUCS=(1<<4);
+ SYNCDELAY;
+
+}
+
+void slave_fifo_init() {
+
+ /* initialization of the slave fifo, used by external logic (the fpga)
+ * to do usb communication with the host */
+
+ /* set bit 0 and 1 - fifo slave config */
+ IFCONFIG|=0x03;
+ SYNCDELAY;
+
+ /* async mode */
+ IFCONFIG|=0x04;
+ SYNCDELAY;
+
+ /* p. 180: must be set to 1 */
+ REVCTL|=((1<<0)|(1<<1));
+ SYNCDELAY;
+
+ /* 8 bit fifo to all endpoints
+ *
+ * ('or' of all these bits define port d functionality)
+ */
+ EP2FIFOCFG&=~(1<<0);
+ SYNCDELAY;
+ EP4FIFOCFG&=~(1<<0);
+ SYNCDELAY;
+ EP6FIFOCFG&=~(1<<0);
+ SYNCDELAY;
+ EP8FIFOCFG&=~(1<<0);
+ SYNCDELAY;
+
+ /* default indexed flag configuration:
+ *
+ * flag a: programmable level
+ * flag b: full
+ * flag c: empty
+ *
+ * todo: -> fixed configuration
+ */
+
+ /* endpoint configuration:
+ *
+ * ep2: bulk out 4x512
+ * ep6: bulk in 4x512
+ *
+ * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
+ * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
+ */
+ EP2CFG=0xa0;
+ SYNCDELAY;
+ EP4CFG&=(~0x80);
+ SYNCDELAY;
+ EP6CFG=0xe0;
+ SYNCDELAY;
+ EP8CFG&=(~0x80);
+ SYNCDELAY;
+
+ /* reset the fifo */
+ FIFORESET=0x80; /* nak all transfers */
+ SYNCDELAY;
+ FIFORESET=0x02; /* reset ep2 */
+ SYNCDELAY;
+ FIFORESET=0x06; /* reset ep6 */
+ SYNCDELAY;
+ FIFORESET=0x00; /* restore normal operation */
+ SYNCDELAY;
+
+ /* auto in/out, no cpu interaction! auto in len = 512 */
+ EP2FIFOCFG|=(1<<4);
+ SYNCDELAY;
+ EP6FIFOCFG|=(1<<3);
+ SYNCDELAY;
+ EP6AUTOINLENH=(1<<1);
+ SYNCDELAY;
+ EP6AUTOINLENL=0;
+ SYNCDELAY;
+
+}
+
+void ep1_init() {
+
+ /* initialize endpoint 1
+ *
+ * used for jtag & control
+ */
+
+ /* endpoint 1 configuration:
+ *
+ * default (valid, bulk) fits!
+ */
+
+ /* arm ep1out, clear ep1out and ep1in stall bit */
+ EP1OUTBC=1;
+ EP1OUTCS&=~STALL;
+ EP1INCS&=~STALL;
+
+}
+
+void fx2_init() {
+
+ /* syncdelay */
+ SYNCDELAY;
+
+ /* cpu init */
+ cpu_init();
+
+ /* power init & power on */
+ power_init();
+ toggle_power();
+
+ /* slave fifo init */
+ slave_fifo_init();
+
+ /* ep1 init */
+ ep1_init();
+
+ /* jtag init */
+ jtag_init();