+ #
+ # concerning irq:
+ # - the ldr is at 0x18
+ # - pc will be 0x18 + 8 at the moment of ldr (pipeline)
+ # - substract 0xff0 => 0xfffff030
+ # - that's the vectored address register
+ # - the vic put in there the address of our service routine
+
+exception_vectors:
+
+ ldr pc, handler_reset
+ ldr pc, handler_undef_instruction
+ ldr pc, handler_soft_ir
+ ldr pc, handler_prefetch_abort
+ ldr pc, handler_data_abort