1 /* Register definitions for Philips CL RC632 RFID Reader IC
3 * (C) 2005 Harald Welte <laforge@gnumonks.org>
5 * Licensed under GNU General Public License, Version 2
9 RC632_REG_PAGE0 = 0x00,
10 RC632_REG_COMMAND = 0x01,
11 RC632_REG_FIFO_DATA = 0x02,
12 RC632_REG_PRIMARY_STATUS = 0x03,
13 RC632_REG_FIFO_LENGTH = 0x04,
14 RC632_REG_SECONDARY_STATUS = 0x05,
15 RC632_REG_INTERRUPT_EN = 0x06,
16 RC632_REG_INTERRUPT_RQ = 0x07,
18 RC632_REG_PAGE1 = 0x08,
19 RC632_REG_CONTROL = 0x09,
20 RC632_REG_ERROR_FLAG = 0x0a,
21 RC632_REG_COLL_POS = 0x0b,
22 RC632_REG_TIMER_VALUE = 0x0c,
23 RC632_REG_CRC_RESULT_LSB = 0x0d,
24 RC632_REG_CRC_RESULT_MSB = 0x0e,
25 RC632_REG_BIT_FRAMING = 0x0f,
27 RC632_REG_PAGE2 = 0x10,
28 RC632_REG_TX_CONTROL = 0x11,
29 RC632_REG_CW_CONDUCTANCE = 0x12,
30 RC632_REG_MOD_CONDUCTANCE = 0x13,
31 RC632_REG_CODER_CONTROL = 0x14,
32 RC632_REG_MOD_WIDTH = 0x15,
33 RC632_REG_MOD_WIDTH_SOF = 0x16,
34 RC632_REG_TYPE_B_FRAMING = 0x17,
36 RC632_REG_PAGE3 = 0x18,
37 RC632_REG_RX_CONTROL1 = 0x19,
38 RC632_REG_DECODER_CONTROL = 0x1a,
39 RC632_REG_BIT_PHASE = 0x1b,
40 RC632_REG_RX_THRESHOLD = 0x1c,
41 RC632_REG_BPSK_DEM_CONTROL = 0x1d,
42 RC632_REG_RX_CONTROL2 = 0x1e,
43 RC632_REG_CLOCK_Q_CONTROL = 0x1f,
45 RC632_REG_PAGE4 = 0x20,
46 RC632_REG_RX_WAIT = 0x21,
47 RC632_REG_CHANNEL_REDUNDANCY = 0x22,
48 RC632_REG_CRC_PRESET_LSB = 0x23,
49 RC632_REG_CRC_PRESET_MSB = 0x24,
50 RC632_REG_TIME_SLOT_PERIOD = 0x25,
51 RC632_REG_MFOUT_SELECT = 0x26,
52 RC632_REG_PRESET_27 = 0x27,
54 RC632_REG_PAGE5 = 0x28,
55 RC632_REG_FIFO_LEVEL = 0x29,
56 RC632_REG_TIMER_CLOCK = 0x2a,
57 RC632_REG_TIMER_CONTROL = 0x2b,
58 RC632_REG_TIMER_RELOAD = 0x2c,
59 RC632_REG_IRQ_PIN_CONFIG = 0x2d,
60 RC632_REG_PRESET_2E = 0x2e,
61 RC632_REG_PRESET_2F = 0x2f,
63 RC632_REG_PAGE6 = 0x30,
65 RC632_REG_PAGE7 = 0x38,
66 RC632_REG_TEST_ANA_SELECT = 0x3a,
67 RC632_REG_TEST_DIGI_SELECT = 0x3d,
70 enum rc632_reg_command {
71 RC632_CMD_IDLE = 0x00,
72 RC632_CMD_WRITE_E2 = 0x01,
73 RC632_CMD_READ_E2 = 0x03,
74 RC632_CMD_LOAD_CONFIG = 0x07,
75 RC632_CMD_LOAD_KEY_E2 = 0x0b,
76 RC632_CMD_AUTHENT1 = 0x0c,
77 RC632_CMD_CALC_CRC = 0x12,
78 RC632_CMD_AUTHENT2 = 0x14,
79 RC632_CMD_RECEIVE = 0x16,
80 RC632_CMD_LOAD_KEY = 0x19,
81 RC632_CMD_TRANSMIT = 0x1a,
82 RC632_CMD_TRANSCIEVE = 0x1e,
83 RC632_CMD_STARTUP = 0x3f,
86 enum rc632_reg_control {
87 RC632_CONTROL_CRYPTO1_ON = 0x08,
88 RC632_CONTROL_POWERDOWN = 0x10,
91 enum rc632_reg_error_flag {
92 RC632_ERR_FLAG_COL_ERR = 0x01,
93 RC632_ERR_FLAG_PARITY_ERR = 0x02,
94 RC632_ERR_FLAG_FRAMING_ERR = 0x04,
95 RC632_ERR_FLAG_CRC_ERR = 0x08,
96 RC632_ERR_FLAG_FIFO_OVERFLOW = 0x10,
97 RC632_ERR_FLAG_ACCESS_ERR = 0x20,
98 RC632_ERR_FLAG_KEY_ERR = 0x40,
101 enum rc632_reg_tx_control {
102 RC632_TXCTRL_TX1_RF_EN = 0x01,
103 RC632_TXCTRL_TX2_RF_EN = 0x02,
104 RC632_TXCTRL_TX2_CW = 0x04,
105 RC632_TXCTRL_TX2_INV = 0x08,
106 RC632_TXCTRL_FORCE_100_ASK = 0x10,
108 RC632_TXCTRL_MOD_SRC_LOW = 0x00,
109 RC632_TXCTRL_MOD_SRC_HIGH = 0x20,
110 RC632_TXCTRL_MOD_SRC_INT = 0x40,
111 RC632_TXCTRL_MOD_SRC_MFIN = 0x60,
114 enum rc632_reg_coder_control {
115 RC632_CDRCTRL_TXCD_NRZ = 0x00,
116 RC632_CDRCTRL_TXCD_14443A = 0x01,
117 RC632_CDRCTRL_TXCD_ICODE_STD = 0x04,
119 #define RC632_CDRCTRL_RATE_MASK 0x38
120 RC632_CDRCTRL_RATE_848K = 0x00,
121 RC632_CDRCTRL_RATE_424K = 0x08,
122 RC632_CDRCTRL_RATE_212K = 0x10,
123 RC632_CDRCTRL_RATE_106K = 0x18,
124 RC632_CDRCTRL_RATE_14443B = 0x20,
125 RC632_CDRCTRL_RATE_15693 = 0x28,
126 RC632_CDRCTRL_RATE_ICODE_FAST = 0x30,
129 enum rc632_erg_type_b_framing {
130 RC632_TBFRAMING_SOF_10L_2H = 0x00,
131 RC632_TBFRAMING_SOF_10L_3H = 0x01,
132 RC632_TBFRAMING_SOF_11L_2H = 0x02,
133 RC632_TBFRAMING_SOF_11L_3H = 0x03,
135 RC632_TBFRAMING_EOF_10 = 0x00,
136 RC632_TBFRAMING_EOF_11 = 0x20,
138 RC632_TBFRAMING_NO_TX_SOF = 0x80,
139 RC632_TBFRAMING_NO_TX_EOF = 0x40,
141 #define RC632_TBFRAMING_SPACE_SHIFT 2
142 #define RC632_TBFRAMING_SPACE_MASK 7
144 enum rc632_reg_rx_control1 {
145 RC632_RXCTRL1_GAIN_20DB = 0x00,
146 RC632_RXCTRL1_GAIN_24DB = 0x01,
147 RC632_RXCTRL1_GAIN_31DB = 0x02,
148 RC632_RXCTRL1_GAIN_35DB = 0x03,
150 RC632_RXCTRL1_LP_OFF = 0x04,
151 RC632_RXCTRL1_ISO15693 = 0x08,
152 RC632_RXCTRL1_ISO14443 = 0x10,
154 #define RC632_RXCTRL1_SUBCP_MASK 0xe0
155 RC632_RXCTRL1_SUBCP_1 = 0x00,
156 RC632_RXCTRL1_SUBCP_2 = 0x20,
157 RC632_RXCTRL1_SUBCP_4 = 0x40,
158 RC632_RXCTRL1_SUBCP_8 = 0x60,
159 RC632_RXCTRL1_SUBCP_16 = 0x80,
162 enum rc632_reg_decoder_control {
163 RC632_DECCTRL_MANCHESTER = 0x00,
164 RC632_DECCTRL_BPSK = 0x01,
166 RC632_DECCTRL_RX_INVERT = 0x04,
168 RC632_DECCTRL_RXFR_ICODE = 0x00,
169 RC632_DECCTRL_RXFR_14443A = 0x08,
170 RC632_DECCTRL_RXFR_15693 = 0x10,
171 RC632_DECCTRL_RXFR_14443B = 0x18,
173 RC632_DECCTRL_ZEROAFTERCOL = 0x20,
175 RC632_DECCTRL_RX_MULTIPLE = 0x40,
178 enum rc632_reg_bpsk_dem_control {
179 RC632_BPSKD_TAUB_SHIFT = 0x00,
180 RC632_BPSKD_TAUB_MASK = 0x03,
182 RC632_BPSKD_TAUD_SHIFT = 0x02,
183 RC632_BPSKD_TAUD_MASK = 0x03,
185 RC632_BPSKD_FILTER_AMP_DETECT = 0x10,
186 RC632_BPSKD_NO_RX_EOF = 0x20,
187 RC632_BPSKD_NO_RX_EGT = 0x40,
188 RC632_BPSKD_NO_RX_SOF = 0x80,
191 enum rc632_reg_rx_control2 {
192 RC632_RXCTRL2_DECSRC_LOW = 0x00,
193 RC632_RXCTRL2_DECSRC_INT = 0x01,
194 RC632_RXCTRL2_DECSRC_SUBC_MFIN = 0x10,
195 RC632_RXCTRL2_DECSRC_BASE_MFIN = 0x11,
197 RC632_RXCTRL2_AUTO_PD = 0x40,
198 RC632_RXCTRL2_CLK_I = 0x80,
199 RC632_RXCTRL2_CLK_Q = 0x00,
202 enum rc632_reg_channel_redundancy {
203 RC632_CR_PARITY_ENABLE = 0x01,
204 RC632_CR_PARITY_ODD = 0x02,
205 RC632_CR_TX_CRC_ENABLE = 0x04,
206 RC632_CR_RX_CRC_ENABLE = 0x08,
207 RC632_CR_CRC8 = 0x10,
208 RC632_CR_CRC3309 = 0x20,