1 ;***************************************************************************
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2 ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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5 ;* File Name : "m64def.inc"
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6 ;* Title : Register/Bit Definitions for the ATmega604
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7 ;* Date : April 16th, 2002
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9 ;* Support telephone : +47 72 88 43 88 (ATMEL Norway)
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10 ;* Support fax : +47 72 88 43 99 (ATMEL Norway)
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11 ;* Support E-mail : support@atmel.no
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12 ;* Target MCU : ATmega64
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15 ;* When including this file in the assembly program file, all I/O register
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16 ;* names and I/O register bit names appearing in the data book can be used.
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17 ;* In addition, the six registers forming the three data pointers X, Y and
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18 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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19 ;* SRAM is also defined
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21 ;* The Register names are represented by their hexadecimal address.
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23 ;* The Register Bit names are represented by their bit number (0-7).
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25 ;* Please observe the difference in using the bit names with instructions
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26 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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27 ;* (skip if bit in register set/cleared). The following example illustrates
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30 ;* in r16,PORTB ;read PORTB latch
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31 ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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32 ;* out PORTB,r16 ;output to PORTB
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34 ;* in r16,TIFR ;read the Timer Interrupt Flag Register
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35 ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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36 ;* rjmp TOV0_is_set ;jump if set
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37 ;* ... ;otherwise do something else
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38 ;***************************************************************************
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40 ;**** Specify Device ****
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43 ;*****************************************************************************
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44 ; I/O Register Definitions
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45 ;*****************************************************************************
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47 ;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
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90 .equ SPMCR = $68 ; old name for SPMCSR
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97 ;**** I/O Register Definitions ($3F-$00) ****
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104 .equ GIMSK = $39 ; old name for EIMSK
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105 .equ GICR = $39 ; old name for EIMSK
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107 .equ GIFR = $38 ; old name for EIFR
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129 .equ OCDR = $22 ; New
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131 .equ SFIOR = $20 ; New
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143 .equ DDRC = $14 ; New
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144 .equ PINC = $13 ; New
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167 ;*****************************************************************************
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169 ;*****************************************************************************
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171 ; **** MCU Control ****
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206 .equ ASB = 6 ; backwards compatiblity
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207 .equ ASRE = 4 ; backwards compatiblity
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246 ; **** Analog to Digital Converter ****
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273 ;**** Analog Comparator ****
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285 ; **** External Interrupts ****
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326 ; **** Timer Interrupts ****
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363 ; **** Asynchronous Timer ****
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370 ; **** Timer 0 ****
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383 ; **** Timer 1 ****
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391 .equ PWM11 = 1 ; OBSOLETE! Use WGM11
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392 .equ PWM10 = 0 ; OBSOLETE! Use WGM10
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399 .equ CTC11 = 4 ; OBSOLETE! Use WGM13
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400 .equ CTC10 = 3 ; OBSOLETE! Use WGM12
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412 ; **** Timer 2 ****
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425 ; **** Timer 3 ****
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433 .equ PWM31 = 1 ; OBSOLETE! Use WGM31
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434 .equ PWM30 = 0 ; OBSOLETE! Use WGM30
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438 ; **** TCCR3B ****
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441 .equ CTC31 = 4 ; OBSOLETE! Use WGM33
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442 .equ CTC30 = 3 ; OBSOLETE! Use WGM32
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454 ; **** Watchdog Timer ****
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457 .equ WDTOE = 4 ; For Mega103 compability
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463 ; **** EEPROM Control Register ****
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470 ; **** USART 0 and USART 1 ****
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471 ; **** (UCSRA0/1) ****
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477 .equ PE = 2 ; OBSOLETED!
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481 ; **** (UCSR0A) ****
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491 ; **** (UCSR1A) ****
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501 ; **** (UCSRB0/1) ****
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511 ; **** (UCSR0B) ****
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521 ; **** (UCSR1B) ****
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531 ; **** (UCSRC0/1) ****
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540 ; **** (UCSR0C) ****
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549 ; **** (UCSR1C) ****
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575 ; **** I2C/TWI ****
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584 .equ I2C_TST = 1 ; Present in core test mode only. Write Only.
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602 .equ TWC_TST = 1 ; Present in core test mode only. Write Only.
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876 ;*****************************************************************************
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877 ; CPU Register Declarations
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878 ;*****************************************************************************
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880 .def XL = r26 ; X pointer low
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881 .def XH = r27 ; X pointer high
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882 .def YL = r28 ; Y pointer low
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883 .def YH = r29 ; Y pointer high
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884 .def ZL = r30 ; Z pointer low
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885 .def ZH = r31 ; Z pointer high
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888 ;*****************************************************************************
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889 ; Data Memory Declarations
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890 ;*****************************************************************************
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892 .equ RAMEND = $10ff ; Highest internal data memory (SRAM) address.
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893 .equ EEPROMEND = $07ff ; Highest EEPROM address.
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895 ;*****************************************************************************
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896 ; Program Memory Declarations
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897 ;*****************************************************************************
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899 .equ FLASHEND = $7FFF ; Highest program memory (flash) address
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900 ; (When addressed as 16 bit words)
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902 ;**** Boot Vectors ****
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904 ; /--\/--\/--\/--\
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905 .equ SMALLBOOTSTART = 0b0111111000000000 ; ($7E00) Smallest boot block is 512W
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906 .equ SECONDBOOTSTART = 0b0111110000000000 ; ($7C00) 2'nd boot block size is 1KW
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907 .equ THIRDBOOTSTART = 0b0111100000000000 ; ($7800) Third boot block size is 2KW
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908 .equ LARGEBOOTSTART = 0b0111000000000000 ; ($7000) Largest boot block is 4KW
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911 ;**** Page Size ****
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912 .equ PAGESIZE = 128 ; Number of WORDS in a page
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915 ;**** Interrupt Vectors ****
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916 .equ INT0addr = $002 ; External Interrupt0 Vector Address
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917 .equ INT1addr = $004 ; External Interrupt1 Vector Address
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918 .equ INT2addr = $006 ; External Interrupt2 Vector Address
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919 .equ INT3addr = $008 ; External Interrupt3 Vector Address
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920 .equ INT4addr = $00a ; External Interrupt4 Vector Address
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921 .equ INT5addr = $00c ; External Interrupt5 Vector Address
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922 .equ INT6addr = $00e ; External Interrupt6 Vector Address
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923 .equ INT7addr = $010 ; External Interrupt7 Vector Address
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924 .equ OC2addr = $012 ; Output Compare2 Interrupt Vector Address
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925 .equ OVF2addr = $014 ; Overflow2 Interrupt Vector Address
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926 .equ ICP1addr = $016 ; Input Capture1 Interrupt Vector Address
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927 .equ OC1Aaddr = $018 ; Output Compare1A Interrupt Vector Address
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928 .equ OC1Baddr = $01a ; Output Compare1B Interrupt Vector Address
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929 .equ OVF1addr = $01c ; Overflow1 Interrupt Vector Address
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930 .equ OC0addr = $01e ; Output Compare0 Interrupt Vector Address
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931 .equ OVF0addr = $020 ; Overflow0 Interrupt Vector Address
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932 .equ SPIaddr = $022 ; SPI Interrupt Vector Address
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933 .equ URXC0addr = $024 ; USART0 Receive Complete Interrupt Vector Address
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934 .equ UDRE0addr = $026 ; USART0 Data Register Empty Interrupt Vector Address
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935 .equ UTXC0addr = $028 ; USART0 Transmit Complete Interrupt Vector Address
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936 .equ ADCCaddr = $02a ; ADC Conversion Complete Handle
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937 .equ ERDYaddr = $02c ; EEPROM Write Complete Handle
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938 .equ ACIaddr = $02e ; Analog Comparator Interrupt Vector Address
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940 .equ OC1Caddr = $030 ; Output Compare1C Interrupt Vector Address
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941 .equ ICP3addr = $032 ; Input Capture3 Interrupt Vector Address
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942 .equ OC3Aaddr = $034 ; Output Compare3A Interrupt Vector Address
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943 .equ OC3Baddr = $036 ; Output Compare3B Interrupt Vector Address
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944 .equ OC3Caddr = $038 ; Output Compare3C Interrupt Vector Address
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945 .equ OVF3addr = $03A ; Overflow3 Interrupt Vector Address
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946 .equ URXC1addr = $03C ; USART1 Receive Complete Interrupt Vector Address
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947 .equ UDRE1addr = $03E ; USART1 Data Register Empty Interrupt Vector Address
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948 .equ UTXC1addr = $040 ; USART1 Transmit Complete Interrupt Vector Address
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949 .equ I2Caddr = $042 ; I2C Interrupt Vector Address
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950 .equ TWIaddr = $042 ; TWI Interrupt Vector Address
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951 .equ SPMRaddr = $044 ; Store Program Memory Ready Interrupt Vector Address
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954 ;**** End of File ****
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