4 * author: hackbard@hackdaworld.org
7 * - switch on board power (done)
8 * - allow high speed bulk usb transfer
13 /* constant definitions */
19 /* type definitions */
20 typedef unsigned char u8;
21 typedef unsigned short u16;
22 typedef unsigned int u32;
28 /* general configuration */
29 xdata at 0xe600 volatile u8 CPUCS;
30 xdata at 0xe601 volatile u8 IFCONFIG;
32 /* endpoint configuration */
33 xdata at 0xe604 volatile u8 FIFORESET;
34 xdata at 0xe60b volatile u8 REVCTL;
35 xdata at 0xe612 volatile u8 EP2CFG;
36 xdata at 0xe613 volatile u8 EP4CFG;
37 xdata at 0xe614 volatile u8 EP6CFG;
38 xdata at 0xe615 volatile u8 EP8CFG;
39 xdata at 0xe618 volatile u8 EP2FIFOCFG;
40 xdata at 0xe619 volatile u8 EP4FIFOCFG;
41 xdata at 0xe61a volatile u8 EP6FIFOCFG;
42 xdata at 0xe61b volatile u8 EP8FIFOCFG;
43 xdata at 0xe620 volatile u8 EP2AUTOINLENH;
44 xdata at 0xe621 volatile u8 EP2AUTOINLENL;
45 xdata at 0xe624 volatile u8 EP6AUTOINLENH;
46 xdata at 0xe625 volatile u8 EP6AUTOINLENL;
48 /* special funtion registers */
52 /* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
53 * and some others (p. 438).
54 * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
55 #define SYNCDELAY _asm \
56 nop; nop; nop; nop; nop; nop; nop; nop; \
57 nop; nop; nop; nop; nop; nop; nop; nop; \
62 /* pin 7 of port d connected to mosfet gate controlling the board power
64 * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
67 /* configure pin 7 of port d as output */
75 /* toggle high/low state of the mosfet gate */
88 /* cpu initialization: (0x10)
90 * - none inverted signal
99 void slave_fifo_init() {
101 /* initialization of the slave fifo, used by external logic (the fpga)
102 * to do usb communication with the host */
104 /* set bit 0 and 1 - fifo slave config */
112 /* p. 180: must be set to 1 */
113 REVCTL|=((1<<0)|(1<<1));
116 /* 8 bit fifo to all endpoints
118 * ('or' of all these bits define port d functionality)
129 /* default indexed flag configuration:
131 * flag a: programmable level
135 * todo: -> fixed configuration
138 /* endpoint configuration:
140 * ep2: bulk out 4x512
143 * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
144 * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
156 FIFORESET=0x80; /* nak all transfers */
158 FIFORESET=0x02; /* reset ep2 */
160 FIFORESET=0x06; /* reset ep6 */
162 FIFORESET=0x00; /* restore normal operation */
165 /* auto in/out, no cpu interaction! auto in len = 512 */
170 EP6AUTOINLENH=(1<<1);
179 /* initialize endpoint 1
181 * used for jtag & control
184 /* endpoint 1 configuration:
186 * default (valid, bulk) fits!
196 /* power init & power on */
200 /* slave fifo init */
209 /* initialize the fx2 */