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small ep mods for fx2, added xilprg patch to support bitbanging the fx2
[my-code/fpga.git]
/
fx2
/
fx2.c
diff --git
a/fx2/fx2.c
b/fx2/fx2.c
index
c52c81b
..
90e40e9
100644
(file)
--- a/
fx2/fx2.c
+++ b/
fx2/fx2.c
@@
-40,6
+40,8
@@
xdata at 0xe618 volatile u8 EP2FIFOCFG;
xdata at 0xe619 volatile u8 EP4FIFOCFG;
xdata at 0xe61a volatile u8 EP6FIFOCFG;
xdata at 0xe61b volatile u8 EP8FIFOCFG;
xdata at 0xe619 volatile u8 EP4FIFOCFG;
xdata at 0xe61a volatile u8 EP6FIFOCFG;
xdata at 0xe61b volatile u8 EP8FIFOCFG;
+xdata at 0xe620 volatile u8 EP2AUTOINLENH;
+xdata at 0xe621 volatile u8 EP2AUTOINLENL;
xdata at 0xe624 volatile u8 EP6AUTOINLENH;
xdata at 0xe625 volatile u8 EP6AUTOINLENL;
xdata at 0xe624 volatile u8 EP6AUTOINLENH;
xdata at 0xe625 volatile u8 EP6AUTOINLENL;
@@
-64,6
+66,7
@@
void power_init() {
/* configure pin 7 of port d as output */
OED|=(1<<7);
/* configure pin 7 of port d as output */
OED|=(1<<7);
+ SYNCDELAY;
}
}
@@
-76,6
+79,8
@@
void toggle_power() {
else
IOD|=(1<<7);
else
IOD|=(1<<7);
+ SYNCDELAY;
+
}
void cpu_init() {
}
void cpu_init() {
@@
-132,20
+137,19
@@
void slave_fifo_init() {
/* endpoint configuration:
*
/* endpoint configuration:
*
- * ep2: bulk
in
4x512
- * ep6: bulk
out
4x512
+ * ep2: bulk
out
4x512
+ * ep6: bulk
in
4x512
*
* 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
* 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
*
* 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
* 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
- * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
*/
EP2CFG=0xa0;
SYNCDELAY;
*/
EP2CFG=0xa0;
SYNCDELAY;
- EP4CFG
=0x01
;
+ EP4CFG
&=(~0x80)
;
SYNCDELAY;
EP6CFG=0xe0;
SYNCDELAY;
SYNCDELAY;
EP6CFG=0xe0;
SYNCDELAY;
- EP8CFG
=0x01
;
+ EP8CFG
&=(~0x80)
;
SYNCDELAY;
/* reset the fifo */
SYNCDELAY;
/* reset the fifo */