X-Git-Url: https://hackdaworld.org/gitweb/?p=my-code%2Fatmel.git;a=blobdiff_plain;f=monolyzer%2Fmain.asm;h=c2482c744073975c4bd2b0f714c890cd1c0ef507;hp=b5ed20c87e39f101d342d92dced8a0a4fe6c85fa;hb=93885b52eac89908bd09246c2b2aae0a09b7cff2;hpb=a023fa740e46e4cd9c6f6d13349de9629017b654

diff --git a/monolyzer/main.asm b/monolyzer/main.asm
index b5ed20c..c2482c7 100644
--- a/monolyzer/main.asm
+++ b/monolyzer/main.asm
@@ -12,10 +12,14 @@
 .def	tmp1		= r16
 .def	tmp2		= r17
 .def	uart_rxtx	= r18
-.def	bcount		= r19
-.def	scount		= r20
-.def	data		= r21
-.def	state		= r22
+.def	count		= r19
+.def	state		= r20
+.def	scount		= r21
+.def	input		= r22
+.def	save		= r23
+
+;.define FLOODME
+;.define S_FLOODME
 
 ;
 ; interrupts
@@ -25,7 +29,7 @@
 rjmp INIT
 
 ; INT0
-reti
+rjmp INT0_IR
 
 ; INT1
 reti
@@ -37,13 +41,13 @@ reti
 reti
 
 ; T1 OVF1
-reti
+rjmp T1_OVF_IR
 
 ; T0 OVF0
-rjmp T0_OVF
+reti
 
 ; UART RX
-rjmp UART_RECEIVE
+reti
 
 ; UART UDRE
 reti
@@ -88,8 +92,8 @@ INIT:
 	; gio port init
 	rcall PORT_INIT
 
-	; timer0 init
-	rcall TIMER0_INIT
+	; timer1 init
+	rcall TIMER1_INIT_64
 
 	; uart init
 	rcall UART_INIT
@@ -105,42 +109,70 @@ INIT:
 	out SPL,tmp1
 
 	; more init
-	ldi bcount,0
-	ldi scount,0
-	ldi data,0x00
-	ldi state,1
+	ldi count,0
+	ldi state,0
 
 	; storage pointer
 	ldi ZL,low(STORAGE)
 	ldi ZH,high(STORAGE)
 
+	ldi scount,0
+	ldi tmp1,0x23
+INIT_STORAGE:
+	; init storage
+	st Z+,tmp1
+	st Z+,tmp1
+	add scount,one
+	cpi scount,55
+	brne INIT_STORAGE
+
+	; storage pointer again
+	ldi ZL,low(STORAGE)
+	ldi ZH,high(STORAGE)
+
 	; signal ready output
 	ldi uart_rxtx,0x72
 	rcall UART_TX
 
+.ifdef FLOODME
+DEBUG_PORT:
+	;rcall UART_RX
+	ldi scount,0
+DEBUG_PORT_LOOP:
+	lsl uart_rxtx
+	in tmp1,PIND
+	sbrc tmp1,2
+	add uart_rxtx,one
+	add scount,one
+	cpi scount,8
+	brne DEBUG_PORT_LOOP
+	rcall UART_TX
+	rjmp DEBUG_PORT
+.endif
+
+.ifdef S_FLOODME
+DEBUG_PORT:
+	ldi uart_rxtx,0x30
+	in tmp1,PIND
+	sbrc tmp1,2
+	add uart_rxtx,one
+	rcall UART_TX
+	rjmp DEBUG_PORT
+.endif
+	; enable interrupts
+	rcall INT0_IR_CONF_R
+	rcall INT0_IR_ENABLE
+
 	; global interrupt enable
 	sei 
 
 MAIN:
 
-WAIT_FOR_HIGH:
-
-	; start as soon as we get a high signal
-	in tmp1,PORTB
-	sbrs tmp1,0
-	rjmp WAIT_FOR_HIGH
-
-	; timer0 interrupt enable
-	rcall TIMER0_INT_INIT
-	
 SAMPLE:
 
-	; sample as long as there is storage capacity
-	sbrs state,0
-	rjmp SAMPLE
-
-	; timer0 interrupt disable
-	rcall TIMER0_INT_END
+	; sample as long as there is storage capacity and signal
+	cpi state,10
+	brne SAMPLE
 
 	; signal finish
 	ldi uart_rxtx,0x66
@@ -152,31 +184,49 @@ IDLE:
 	rcall UART_RX
 
 	; decode instruction
-	cpi uart_rxtx,0x52
+	cpi uart_rxtx,0x72
 	breq RESET
-	cpi uart_rxtx,0x54
+	cpi uart_rxtx,0x74
 	breq TRANSFER
+	cpi uart_rxtx,0x73
+	breq SINGLE_SAMPLE
 
 	rjmp IDLE
 
+SINGLE_SAMPLE:
+
+	; sample port d pin 2 and output via uart
+	ldi uart_rxtx,0x30
+	in tmp2,PIND
+	sbrc tmp2,2
+	ldi uart_rxtx,0x31
+	rcall UART_TX
+	rjmp IDLE
+
 TRANSFER:
 
 	; reset storage pointer
 	ldi ZL,low(STORAGE)
 	ldi ZH,high(STORAGE)
-	ldi scount,0
+	ldi scount,1
+
+	; transmit number of sampled words
+	mov uart_rxtx,count
+	rcall UART_TX
 
 TRANSFER_LOOP:
 
-	; transmit storage
+	; send data and counter
+	ld uart_rxtx,Z+
+	rcall UART_TX
 	ld uart_rxtx,Z+
 	rcall UART_TX
 
 	; count sent data
 	add scount,one
 
-	; check amount of sent data
-	cpi scount,128
+	; check amount of data
+	cpi scount,56
 	breq IDLE
 
 	rjmp TRANSFER_LOOP
@@ -190,46 +240,81 @@ TRANSFER_LOOP:
 ; interrupt routines
 ;
 
-T0_OVF:
+INT0_IR:
 
-	; debug output
-	; cbi PORTD,3
+	in save,SREG
 
-	; read port
-	in tmp1,PORTB
-	sbrc tmp1,0
-	add data,one
+	cli
 
-	; increase and check bit counter
-	add bcount,one
-	cpi bcount,8
-	brne EXIT_T0_OVF
-	
-	; store another byte into sram
-	st Z+,data
-	ldi bcount,0
-	add scount,one
+	; get timer value
+	in tmp1,TCNT1L
+	in tmp2,TCNT1H
 
-	; check for left capacity
-	cpi scount,128
-	brne EXIT_T0_OVF
-	ldi state,0
+	; reset timer
+	ldi tmp1,0
+	out TCNT1H,tmp1
+	out TCNT1L,tmp1
 
-	; debug output
-	; sbi PORTD,3
+	; check for running state
+	cpi state,5
+	breq INT0_RUN
 
-EXIT_T0_OVF:
+	; reconfigure int0
+	rcall INT0_IR_CONF_FR
+	ldi state,5
+	rcall TIMER1_INT_ENABLE
 
-	; shift data bits
-	; in any case => there is always a zero at lsb
-	lsl data
+	rjmp LEAVE_INT0_IR
+
+INT0_RUN:
+
+	; write timer value into sram
+	st Z+,tmp2
+	st Z+,tmp1
+
+	; inc counter
+	add count,one
 	
-	reti
+	; check for left capacity
+	cpi count,55
+	brne LEAVE_INT0_IR
+
+	; indicate end of 'c'apacity
+	ldi uart_rxtx,0x63
+	rcall UART_TX
 
-UART_RECEIVE:
+	; exit sampling
+	ldi state,10
+
+	; leave all interrupts cleared
+	rjmp EXIT_INT0_IR
+
+LEAVE_INT0_IR:
+
+	sei
+
+EXIT_INT0_IR:
+
+	out SREG,save
 
 	reti
 
+T1_OVF_IR:
+
+	in save,SREG
+
+	cli
+
+	; indicate 'o'verflow end
+	ldi uart_rxtx,0x6f
+	rcall UART_TX
+
+	; exit sampling
+	ldi state,10
+
+	out SREG,save
+
+	reti
 
 ;
 ; sram
@@ -237,6 +322,5 @@ UART_RECEIVE:
 
 .dseg
 
-STORAGE: .byte 128
-
+STORAGE: .byte 110