timer interrupts hopefully work now (pwm and isr not yet working!)

diff --git a/betty/betty.c b/betty/betty.c
index 3b29d2e..24ea2eb 100644 (file)
--- a/betty/betty.c
+++ b/betty/betty.c
@@ -192,9 +192,11 @@ int main() {
        // timer interrupt
        interrupt_tc_config(INTERRUPT_TC0,INTERRUPT_TC_MODE_T,0,0);
        interrupt_tc_match_config(INTERRUPT_TC0,INTERRUPT_M0,120,
-                                 INTERRUPT_TC_MATCH_IR|INTERRUPT_TC_MATCH_RESET);
-       interrupt_tc_ir_set(INTERRUPT_TC0,INTERRUPT_M0);
-       interrupt_enable(INTERRUPT_PWM,INTERRUPT_MODE_VIRQ,1,(u32)&set_sample);
+                                 INTERRUPT_TC_MATCH_IR|
+                                 INTERRUPT_TC_MATCH_RESET);
+       interrupt_tc_ir_set(INTERRUPT_TC0,INTERRUPT_MATCH0);
+       interrupt_enable(INTERRUPT_TIMER0,INTERRUPT_MODE_VIRQ,
+                        1,(u32)&set_sample);
 
        /* pwm init */
        pwm_set_rate_and_prescaler(0xff,0);

diff --git a/betty/interrupts.c b/betty/interrupts.c
index ed33c15..24159c0 100644 (file)
--- a/betty/interrupts.c
+++ b/betty/interrupts.c
@@ -158,11 +158,13 @@ void interrupt_tc_config(u8 tcnum,u8 mode,u8 cap,u32 psv) {
 
        if(tcnum==0) {
                T0TCR=0x03;
+               T0TC=0;
                T0CTCR=mode|(cap<<2);
                T0PR=psv;
        }
        else {
                T1TCR=0x03;
+               T1TC=0;
                T1CTCR=mode|(cap<<2);
                T1PR=psv;
        }

diff --git a/betty/interrupts.h b/betty/interrupts.h
index 0d8266c..0ce073b 100644 (file)
--- a/betty/interrupts.h
+++ b/betty/interrupts.h
@@ -50,6 +50,9 @@
 #define INTERRUPT_EXT2                 2
 #define INTERRUPT_EXT3                 3
 
+#define INTERRUPT_TC0                  0
+#define INTERRUPT_TC1                  1
+
 #define INTERRUPT_TC_MODE_T            0x00
 #define INTERRUPT_TC_MODE_CR           0x01
 #define INTERRUPT_TC_MODE_CF           0x02
@@ -59,26 +62,28 @@
 #define INTERRUPT_TC_MATCH_RESET       0x02
 #define INTERRUPT_TC_MATCH_STOP                0x04
 
+#define INTERRUPT_M0                   0
+#define INTERRUPT_M1                   1
+#define INTERRUPT_M2                   2
+#define INTERRUPT_M3                   3
+
 #define INTERRUPT_TC_CAPT_R            0x01
 #define INTERRUPT_TC_CAPT_F            0x02
 #define INTERRUPT_TC_CAPT_I            0x04
 
-#define INTERRUPT_CAP0                 0x00
-#define INTERRUPT_CAP1                 0x01
-#define INTERRUPT_CAP2                 0x02
-#define INTERRUPT_CAP3                 0x03
-
-#define INTERRUPT_M0                   0x01
-#define INTERRUPT_M1                   0x02
-#define INTERRUPT_M2                   0x04
-#define INTERRUPT_M3                   0x08
-#define INTERRUPT_C0                   0x10
-#define INTERRUPT_C1                   0x20
-#define INTERRUPT_C2                   0x40
-#define INTERRUPT_C3                   0x80
-
-#define INTERRUPT_TC0                  0
-#define INTERRUPT_TC1                  1
+#define INTERRUPT_C0                   0
+#define INTERRUPT_C1                   1
+#define INTERRUPT_C2                   2
+#define INTERRUPT_C3                   3
+
+#define INTERRUPT_MATCH0               0x01
+#define INTERRUPT_MATCH1               0x02
+#define INTERRUPT_MATCH2               0x04
+#define INTERRUPT_MATCH3               0x08
+#define INTERRUPT_CAP0                 0x10
+#define INTERRUPT_CAP1                 0x20
+#define INTERRUPT_CAP2                 0x40
+#define INTERRUPT_CAP3                 0x80
 
 #define INTERRUPT_SET                  0x00
 #define INTERRUPT_USED                 0x01