From: hackbard Date: Mon, 26 Feb 2007 17:09:30 +0000 (+0000) Subject: added syncdelays + cpu init X-Git-Url: https://hackdaworld.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6b7ac2a1220c38d01b25fb8a3c9ec649e9398fda;p=my-code%2Ffpga.git added syncdelays + cpu init --- diff --git a/fx2/fx2.c b/fx2/fx2.c index fcb3dd4..c52c81b 100644 --- a/fx2/fx2.c +++ b/fx2/fx2.c @@ -3,9 +3,9 @@ * * author: hackbard@hackdaworld.org * - * number of priorities: - * - switch on board power - * - allow high speed usb transfer + * feature list: + * - switch on board power (done) + * - allow high speed bulk usb transfer * - do jtag * */ @@ -55,9 +55,9 @@ sfr at 0xb0 IOD; nop; nop; nop; nop; nop; nop; nop; nop; \ nop; _endasm -void power_on() { +void power_init() { - /* high level must be applied to the mosfet gate for power on + /* pin 7 of port d connected to mosfet gate controlling the board power * * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf */ @@ -65,8 +65,30 @@ void power_on() { /* configure pin 7 of port d as output */ OED|=(1<<7); - /* pull it high */ - IOD|=(1<<7); +} + +void toggle_power() { + + /* toggle high/low state of the mosfet gate */ + + if((IOD&(1<<7))) + IOD&=~(1<<7); + else + IOD|=(1<<7); + +} + +void cpu_init() { + + /* cpu initialization: (0x10) + * - 48 mhz + * - none inverted signal + * - no clk out + */ + + CPUCS=(1<<4); + SYNCDELAY; + } void slave_fifo_init() { @@ -76,21 +98,28 @@ void slave_fifo_init() { /* set bit 0 and 1 - fifo slave config */ IFCONFIG|=0x03; + SYNCDELAY; /* async mode */ IFCONFIG|=0x04; + SYNCDELAY; /* p. 180: must be set to 1 */ REVCTL|=((1<<0)|(1<<1)); + SYNCDELAY; /* 8 bit fifo to all endpoints * * ('or' of all these bits define port d functionality) */ EP2FIFOCFG&=~(1<<0); + SYNCDELAY; EP4FIFOCFG&=~(1<<0); + SYNCDELAY; EP6FIFOCFG&=~(1<<0); + SYNCDELAY; EP8FIFOCFG&=~(1<<0); + SYNCDELAY; /* default indexed flag configuration: * @@ -111,28 +140,42 @@ void slave_fifo_init() { * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf) */ EP2CFG=0xa0; + SYNCDELAY; EP4CFG=0x01; + SYNCDELAY; EP6CFG=0xe0; + SYNCDELAY; EP8CFG=0x01; + SYNCDELAY; /* reset the fifo */ FIFORESET=0x80; /* nak all transfers */ + SYNCDELAY; FIFORESET=0x02; /* reset ep2 */ + SYNCDELAY; FIFORESET=0x06; /* reset ep6 */ + SYNCDELAY; FIFORESET=0x00; /* restore normal operation */ + SYNCDELAY; /* auto in/out, no cpu interaction! auto in len = 512 */ EP2FIFOCFG|=(1<<4); + SYNCDELAY; EP6FIFOCFG|=(1<<3); + SYNCDELAY; EP6AUTOINLENH=(1<<1); + SYNCDELAY; EP6AUTOINLENL=0; + SYNCDELAY; - /* maybe OUTPKTEND necessary (with skip=1) */ } void ep1_init() { - /* initialize endpoint 1 (will be used for jtag) */ + /* initialize endpoint 1 + * + * used for jtag & control + */ /* endpoint 1 configuration: * @@ -143,13 +186,18 @@ void ep1_init() { void fx2_init() { - /* swicth on power */ - power_on(); + /* cpu init */ + cpu_init(); + + /* power init & power on */ + power_init(); + toggle_power(); /* slave fifo init */ slave_fifo_init(); - /* ep1_init(); */ + /* ep1 init */ + ep1_init(); } void main() {